count6.vhd

来自「一个用vhdl写的时钟代码」· VHDL 代码 · 共 28 行

--------6进制计数器
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity count6 is
port(clk2 : in std_logic;
		 clr2 : in std_logic;
		 carry2 : out std_logic;
		 value2 : out std_logic_vector(3 downto 0));
end entity count6;
-------------------------------------
architecture behave of count6 is 
begin
	process(clk2,clr2)
	variable temp : std_logic_vector(3 downto 0);
	begin
		if clr2='1' then temp :=(others => '0');
			elsif clk2'event and clk2='1' then
			if temp < 5 then temp := temp + 1;
							carry2 <= '0';
				else temp :=(others => '0');
					 carry2 <= '1';
			end if;
		end if;
		value2 <= temp;
	end process;
end architecture behave;