scan.vhd

来自「一个用vhdl写的时钟代码」· VHDL 代码 · 共 44 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
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entity scan is 
   port(clk_scan : in std_logic;
   		data0,data1,data2 : in std_logic_vector(3 downto 0);
        data3,data4,data5 : in std_logic_vector(3 downto 0);
		dataout : out std_logic_vector(3 downto 0);
		choose : out std_logic_vector(5 downto 0));
end entity scan;
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architecture behave of scan is
signal temp : std_logic_vector(2 downto 0);
  begin
count: process(clk_scan)
    begin
   if clk_scan'event and clk_scan='1' then 
   		if temp < 5 then temp <= temp + 1;
   		else temp <= (others =>'0');
   		end if;
   end if;
  end process count;
display: process(temp,clk_scan,
				 data0,data1,data2,
				 data3,data4,data5)
			begin
			case temp is
			when "000" => dataout <= data0;
						  choose <= "000001";
			when "001" => dataout <= data1;
						  choose <= "000010";
			when "010" => dataout <= data2;
						  choose <= "000100";
			when "011" => dataout <= data3;
						  choose <= "001000";
  			when "100" => dataout <= data4;
						  choose <= "010000";
			when "101" => dataout <= data5;
						  choose <= "100000";
			when others => null;
			end case;
	end process display;
end architecture behave;