spi_comment.vhd

有关SPI的vhdl实现。包括SPI官方协议

  signal tx_start      : std_ulogic;
  signal tx_start_r1   : std_ulogic;

begin   ---------------------------------------------------------------

  mosio <= shift_dataout when mosie_lcl='1' and open_drain='0' else
           '0';
--mosio数据输出：被mosie_lcl使能后读出shift_dataout脚的值
  mosie <= mosie_lcl when open_drain='0' else
--open_drain控制mosie_lcl与mosie是否相等
           '1' when mosie_lcl='1' and shift_dataout='0' else
           -- drive low when open drain enabled.
           '0';
  misoo <= shift_dataout when misoe_lcl='1' and open_drain='0' else
           '0'; 
  misoe <= misoe_lcl when open_drain='0' else
           '1' when misoe_lcl='1' and shift_dataout='0' else
           -- drive low when open drain enabled.
           '0';
--对misoe有mosioe_lcl使能控制做出说明  
  misoe_lcl <= '1' when master_mode='0' and slvsel='1' else
               '0'; 
  mosie_lcl <= '1' when master_mode='1' else
               '0';
--misoe和mosie又是由master_mode决定的。master_mode='0'，miso状态，‘1’，mosi状态



  
  -- spi_go initiates a transfer - A write to the DOUT reg in master
  -- mode ignore the CPU write if we're already running.
  spi_go <= '1' when chip_sel='1' and write='1' and addr="00" and
--spi_go='1'设备空闲状态，片选，可写，datain数据接入shift_reg，tx未执行，slvsel_r3标志位
                     tx_run='0' and slvsel_r3='0' else
            '0';
--spi_go='0'为设备正在运行，防止在运行过程中被访问


--移位寄存器
  sr_proc : process(clk) -------------Shift register----------------
  begin
    if (clk'event and clk='1') then
      if (rst='1') then
        shift_reg <= "00000000";   -- sync reset
      else
        if (spi_go='1') then -- don't reload while running
          shift_reg  <= datain;    -- load with data from CPU
        elsif (shift_clk='1') then
          shift_reg <= shift_reg(6 downto 0) & shift_datain;
        end if;
      end if;
    end if;
  end process;


--phase配合延时寄存器
  neg_proc : process(clk) ----------Hold time register--------------
  begin
    if (clk'event and clk='1') then        -- negative edge pipeline DFF
      if (rst='1') then
        shift_negative_edge <= '0';     -- sync reset
      elsif (shift_clk_negedge='1') then
        shift_negative_edge  <= shift_negative_edge_nxt;
      elsif (spi_go='1') then
        shift_negative_edge  <= datain(7); -- preload for phase=0 mode
      end if;
    end if;
  end process;

  shift_negative_edge_nxt <= shift_reg(7) when phase='1' else
                             misoi when master_mode='1' else
                             mosii;

  shift_dataout <= shift_negative_edge when phase='1' else
                   -- add in the negative edge dff on phase=1
                   shift_reg(7);

  shift_datain <= shift_negative_edge when phase='0' else
                  -- insert the neg DFF in phase=0
                  misoi when master_mode='1' else
                  mosii;




--tx运行标志位：tx_start='1'时为'1'，tx_end='1'时为'0'
  tr_proc : process(clk) ---------------TX run------------------
  -- this bit is active while a transmit is running
  begin
    if (clk'event and clk='1') then
      if (rst='1') then
        tx_run <= '0';     -- sync reset
      else
        if (tx_start='1') then
          tx_run  <= '1';
        elsif (tx_end='1') then
          tx_run <= '0';
        end if;
      end if;
    end if;
  end process;


  
--shift_clk计数器
  bc_proc : process (clk)
  begin -------------Bit counter for master mode----------------
    if (clk'event and clk='1') then
      if (rst='1') then -- sync reset
        bit_ctr <= "000"; 
      else
        if (tx_start='1') then
          bit_ctr <= ssel(7 downto 5);
        elsif (shift_clk='1') then
          bit_ctr <= std_ulogic_vector(unsigned(bit_ctr)-1);
 --bit_ctr在tx_start为'1'时由ssel(5-7)设定值，同时随着shift_clk上升沿触发减少
        end if;
      end if;
    end if;
  end process; -- bit counter

  tx_end <= '1' when master_mode='1' and bit_ctr="001"
                     and shift_clk='1' and tx_run='1' else
            '0';
--tx结束标志：mosi状态，bit_ctr="001"，shift_clk上升沿触发，tx_run='1'时tx_end为'1'
  tx_start <= '1' when master_mode='1' and spi_go='1' else
              '0';
--tx开始标志：mosi状态，spi空闲时，tx_start为'1'



    
--控制寄存器
  gjr_proc : process (clk)
  begin        ---------Control Register----------------------
    if (clk'event and clk='1') then
      if (rst='1') then -- sync reset
        ctl_reg <= "00000000"; 
      else
        if (chip_sel='1' and write='1' and addr="01") then -- load
          ctl_reg <= datain;
        end if;
      end if;
    end if;
  end process;
--在addr="01"的情况下用datain输入ctl_reg，6位有效
  -- map the control register to more meaningfull names
  master_mode <= ctl_reg(1);
  open_drain  <= ctl_reg(2);
  polck       <= ctl_reg(3);
  phase       <= ctl_reg(4);
  sel_clk     <= ctl_reg(6 downto 5);
  



--从设备选择器
  s_proc : process (clk)
  begin  ---------Slave Select Register-------------------------
    if (clk'event and clk='1') then
      if (rst='1') then -- sync reset
        ssel <= "00000000"; 
      else
        if (chip_sel='1' and write='1' and addr="11") then -- load
          ssel <= datain;
        end if;
      end if;
    end if;
  end process;
--在addr="11"的情况下用datain输入要选择的slave，0-4选路，5-7位输入bit_ctr
  slvselo <= ssel(4 downto 0);    -- drive the port
--外部选择口，tristate enable for slave selects
  slvsele <= master_mode;

  
--防止多个master同时操作总线
  cf_proc : process (clk)
  begin ---------Collision flag bit---------------------------
    if (clk'event and clk='1') then
      if (rst='1') then
        col_flag <= '0';
      else
        if (master_mode='1' and slvsel_r3='1') then
          col_flag <= '1';        
        elsif (chip_sel='1' and write='1'
               and addr="10" and datain(5)='1') then
          col_flag <= '0';
        end if;
      end if;
    end if;
  end process;



--在传送数据时要写入dout寄存器时置位
  o_proc : process (clk)
  begin ---------OFLOw flag bit------------------------------
    if (clk'event and clk='1') then
      if (rst='1') then
        oflow <= '0';
      else
        if (chip_sel='1' and write='1' and addr="00" and
            -- write to DOUT
            (tx_run='1' or slvsel_r3='1')) then    -- and we're busy
          oflow <= '1';
        elsif (chip_sel='1' and write='1' and addr="10"
               and datain(6)='1') then
          oflow <= '0';
        end if;
      end if;
    end if;
  end process;


  
--中断请求
  elr_proc : process (clk)
  begin ---------IRQ flag bit------------------------------
    if (clk'event and clk='1') then
      if (rst='1') then
        irq_flag <= '0';
      else
        if (tx_end='1' or (slvsel_r2='0' and slvsel_r3='1')) then
          irq_flag <= '1';        
        elsif (chip_sel='1' and write='1' and addr="10"
               and datain(7)='1') then
          irq_flag <= '0';
        end if;
      end if;
    end if;
  end process;
  irq <= irq_flag and ctl_reg(7); -- gate with the IRQENB bit.



--流水线触发器
  flops_proc : process (clk)
  begin      ----------------various pipeline flops---------
    if (clk'event and clk='1') then
      slvsel_r3   <= slvsel_r2;         --slvsel_r3 corresponds to SLVSEL pin
--                              on the VSPI core (note that this is
--                              normally interted at the IO pin). read
--                              only.
      slvsel_r2   <= slvsel_r1;         -- synchronizers
      slvsel_r1   <= slvsel;
 --由外部slvsel管脚同步移位送入slvsel的设定
      sck_r3      <= sck_r2;
      sck_r2      <= sck_r1;            -- synchronizers
      sck_r1      <= not scki xor polck;
      -- select the desired polarity of the slave clk
      tx_start_r1 <= tx_start;
    end if;
  end process;

  

--分频
  dvd_proc : process (clk) 
  begin----------------clock divider for clk generation-------
    -- create a 2x clock which creates 2 pulses.
    -- One for each edge of SCK.
    if (clk'event and clk='1') then
      if (not (tx_run='1' and master_mode='1') or tx_end='1') then
        -- divider only runs when sending data
        dvd_ctr <= "00000";
--dvd_ctr控制所分频率,sel_clk选择所分频率00=8, 01=16, 10=32, 11=64
        dvd2 <= '0';
      else
        if (dvd_ctr="00000") then
          if (sel_clk="00") then
            dvd_ctr <= "00011";
          elsif (sel_clk="01") then
            dvd_ctr <= "00111";
          elsif (sel_clk="10") then
            dvd_ctr <= "01111";
          else
            dvd_ctr <= "11111";
          end if;
          if (tx_start_r1='0') then
            dvd2 <= not dvd2;
          end if;
        else
          dvd_ctr <= std_ulogic_vector(unsigned(dvd_ctr)-1);
        end if;
      end if;
    end if;
  end process; -- dvd
  

  dvd_zero <= '1' when dvd_ctr="00000" else
              '0';
--dvd_zero用来控制分频是否在进行

  
  shift_clk <= dvd_zero and dvd2 and tx_run and not tx_start_r1 
               -- TX_START_R1 prevents data from shifting on the first
               -- clock in POLCK=1 mode which we don't want.We only get
               -- 7 clocks otherwise.
               when master_mode='1' else
               sck_r2 and not sck_r3;

  shift_clk_negedge <= dvd_zero and not dvd2 and tx_run
                       when master_mode='1'
                       else not sck_r2 and sck_r3;

  with addr select
    dataout <= -- dataout multiplexor for register readback
               shift_reg  when "00",
               ctl_reg    when "01",
               status     when "10",
               ssel       when "11",
               "XXXXXXXX" when others;  --关键，减少错误
--用addr控制dataout口读哪个寄存器的数据

  
  -- assemble the bits that make up the status register
  status <= irq_flag & oflow & col_flag & "000" & tx_run & slvsel_r3;
--定义状态寄存器


  
  scke <= master_mode;
--master_mode控制SCK Clock tristate enable.即sck  <= scko  when scke ='1'
  
  scko <= dvd2 xor polck;
--实际管脚。SCK clock output
end rtl;