memory_write_control.vhd

实现了外界显示器的自定义avalon接口设计

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--地址线为3位
--由NIOS控制其值。
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LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;

ENTITY memory_write_control is
  port (clk:				IN std_logic;
        reset_n:			IN std_logic;
        chipselect:			IN std_logic;
        address:			IN std_logic_vector(2 downto 0);
        write:			IN std_logic;
        writedata:			IN std_logic_vector(31 downto 0);
        read:				IN std_logic;
        byteenable:			IN std_logic_vector(3 downto 0);
        readdata:			OUT std_logic_vector(31 downto 0);
	--Memory地址线，数据线，写使能
		memory_addr: 	OUT std_logic_vector(18 downto 0); --memory地址线
		memory_wrdata:	OUT std_logic_vector(7 downto 0);--memory写数据线
		memory_rddata:	IN std_logic_vector(7 downto 0);--memory读数据线
		memory_wren:		OUT std_logic; --memory读写使能,'1'为写，'0'为读
		memory_select:	OUT std_logic;--memory片选使能，0有效
		memory_io_m :        OUT std_logic;-- 1：写寄存器；0：写存储器
		memory_ready	:	IN std_logic);--memory准备信号，0准备好
END memory_write_control;

ARCHITECTURE control_of_memory of memory_write_control IS
  signal memory_addr_reg:  	std_logic_vector(18 downto 0); --设定的memory为512k字节
  signal memory_wrdata_reg:  std_logic_vector(7 downto 0); 
  signal memory_rddata_reg:  	std_logic_vector(7 downto 0); 
  signal memory_wren_reg:  		std_logic_vector(0 downto 0); 
  signal memory_select_reg:  		std_logic_vector(0 downto 0); 
  signal memory_io_m_reg:  		std_logic_vector(0 downto 0); 
  signal memory_ready_reg:  		std_logic_vector(0 downto 0); 



  signal memory_addr_reg_selected:  		std_logic;
  signal memory_wrdata_reg_selected:  	std_logic;
  signal memory_rddata_reg_selected:  	std_logic;
  signal memory_wren_reg_selected:  		std_logic;
  signal memory_select_reg_selected:  		std_logic; 
  signal memory_io_m_reg_selected:  		std_logic; 
  signal memory_ready_reg_selected:  		std_logic; 


BEGIN
--根据address确定操作的寄存器
process(address)	
  begin
    memory_addr_reg_selected<='0';
    memory_wrdata_reg_selected<='0';
    memory_rddata_reg_selected<='0';
    memory_wren_reg_selected<='0';
    memory_select_reg_selected<='0';
    memory_io_m_reg_selected<='0';
    memory_ready_reg_selected<='0';
    case address is
      when "000" => memory_addr_reg_selected<='1';
      when "001" => memory_wrdata_reg_selected<='1';
      when "010" => memory_rddata_reg_selected<='1';
      when "011" => memory_wren_reg_selected<='1';
	when "100" => memory_select_reg_selected<='1';
	 when "101" => memory_io_m_reg_selected<='1';
	when "110" => memory_ready_reg_selected<='1';
      when others => null;
    end case;
  end process;

memory_rddata_reg<=memory_rddata;	--Memory的读数据输出

--地址寄存器的写
process(clk,reset_n)
begin
  if reset_n='0' then memory_addr_reg<=(others=>'0');
  elsif rising_edge(clk) then
    if (write and chipselect and memory_addr_reg_selected)='1' then
       if byteenable(0)='1' then memory_addr_reg(7 downto 0)<=writedata(7 downto 0);end if;
	if byteenable(1)='1' then memory_addr_reg(15 downto 8)<=writedata(15 downto 8);end if;
	if byteenable(2)='1' then memory_addr_reg(18 downto 16)<=writedata(18 downto 16);end if;
 	end if;
  end if;
end process;
memory_addr<=memory_addr_reg;--Memory的地址数据输入

--写数据寄存器的写
process(clk,reset_n)
begin
  if reset_n='0' then memory_wrdata_reg<=(others=>'0');
  elsif rising_edge(clk) then
    if (write and chipselect and memory_wrdata_reg_selected)='1' then
       if byteenable(0)='1' then memory_wrdata_reg(7 downto 0)<=writedata(7 downto 0);end if;
--       if byteenable(1)='1' then memory_wrdata_reg(15 downto 8)<=writedata(15 downto 8);end if;
--       if byteenable(2)='1' then memory_wrdata_reg(23 downto 16)<=writedata(23 downto 16);end if;
--       if byteenable(3)='1' then memory_wrdata_reg(31 downto 24)<=writedata(31 downto 24);end if;
 	end if;
  end if;
end process;
memory_wrdata<=memory_wrdata_reg;--Memory的写数据输入

--读写使能寄存器的写
process(clk,reset_n)
begin
  if reset_n='0' then memory_wren_reg<=(others=>'0');
  elsif rising_edge(clk) then
    if (write and chipselect and memory_wren_reg_selected)='1' then
       if byteenable(0)='1' then memory_wren_reg(0)<=writedata(0);end if;
 	end if;
  end if;
end process;

memory_wren<=memory_wren_reg(0);--Memory的读写使能输入

--片选寄存器的写
process(clk,reset_n)
begin
  if reset_n='0' then memory_select_reg<=(others=>'0');
  elsif rising_edge(clk) then
    if (write and chipselect and memory_select_reg_selected)='1' then
       if byteenable(0)='1' then memory_select_reg(0)<=writedata(0);end if;
 	end if;
  end if;
end process;

memory_select<=memory_select_reg(0);--Memory的片选使能输入

--操做寄存器还是存储器的写
process(clk,reset_n)
begin
  if reset_n='0' then memory_io_m_reg<=(others=>'0');
  elsif rising_edge(clk) then
    if (write and chipselect and memory_io_m_reg_selected)='1' then
       if byteenable(0)='1' then memory_io_m_reg(0)<=writedata(0);end if;
 	end if;
  end if;
end process;
memory_io_m<=memory_io_m_reg(0);--Memory的选择使能输入


--各寄存器的读
process(address,read,memory_addr_reg,memory_wrdata_reg,memory_rddata_reg,memory_wren_reg,memory_select_reg,memory_io_m_reg,memory_ready_reg,chipselect)
begin
    if (read and chipselect)='1' then
      case address is
      when "000"=>readdata<="00000"&"00000000" & memory_addr_reg(18 downto 0);
      when "001"=>readdata<="00000000" & "00000000" & "00000000" & memory_wrdata_reg;
	  when "010"=>readdata<="00000000" & "00000000" & "00000000" &memory_rddata_reg;
	  when "011"=>readdata<="0000000" & "00000000" & "00000000"& "00000000" & memory_wren_reg(0);
	when "100"=>readdata<="0000000" & "00000000" & "00000000"& "00000000" & memory_select_reg(0);
	when "101"=>readdata<="0000000" & "00000000" & "00000000"& "00000000" & memory_io_m_reg(0);
	when "110"=>readdata<="0000000" & "00000000" & "00000000"& "00000000" & memory_ready_reg(0);
	  when others => readdata<=(others=>'0');
	  end case;
	else  readdata <= (others=>'0');
	end if;
  end process;

end control_of_memory;