syscon.vhd

编码器系统

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    19:52:59 07/27/2007 
-- Design Name: 
-- Module Name:    syscon - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity syscon is
port	(	
			clk : in std_logic;
			vd : in std_logic;
			reg_5 : in std_logic_vector(31 downto 0);
			reg_6 : in std_logic_vector(31 downto 0);

			reset : out std_logic;
			ata_reset_n : out std_logic;
			start_ata : out std_logic;

			reset_data_src : out std_logic;
			reset_buf : out std_logic;
			reset_fsm_sdram : out std_logic
		);
end syscon;

architecture Behavioral of syscon is

signal counter : std_logic_vector(31 downto 0) := (others=>'0');
signal counter1 : std_logic_vector(15 downto 0) := (others=>'0');
signal reset_tmp : std_logic := '0';
signal reset_buf_tmp, reset_fsm_sdram_tmp : std_logic :='0';

begin

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process(clk)
begin
if rising_edge(clk) then				-- 10s
	if reg_6=x"00000055" then
		counter <= (others=>'0');
	elsif counter=x"80000000" then
		counter <= counter;
	else
		counter <= counter + 1;
	end if;
end if;
end process;

process(clk)								-- System reset nearly at power up
begin
if rising_edge(clk) then
	if counter<x"00000200" then
		reset_tmp <= '1';
	else
		reset_tmp <= '0';
	end if;
end if;
end process;

reset <= reset_tmp;

process(clk)
begin
if rising_edge(clk) then
	if reg_5=x"00000055" then
		reset_data_src <= '1';
	else
		reset_data_src <= '0';
	end if;
end if;
end process;

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process(clk)								-- ATA Device reset at power up last 1s
begin
if rising_edge(clk) then
	if counter < x"01800000" then
		ata_reset_n <= '0';
	else
		ata_reset_n <= '1';
	end if;
end if;
end process;

process(clk)								-- ATA Device start singal is use to prevent full signal when fifo resets
begin
if rising_edge(clk) then
	if counter = x"00000800" then
		start_ata <= '1';
	else
		start_ata <= '0';
	end if;
end if;
end process;

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process(clk)								-- Short down the vd time ( actual 120us )
begin
if rising_edge(clk) then
	if reset_tmp='1' then
		counter1 <= (others=>'0');
	elsif vd='0' then
		counter1 <= counter1 + 1;
	else
		counter1 <= (others=>'0');
	end if;
end if;
end process;

process(clk)								-- Every image comes, reset the receiving buffers
begin
if rising_edge(clk) then
	if counter1=x"0001" then			-- Coming faster than reset_buf
		reset_fsm_sdram_tmp <= '1';		
	else
		reset_fsm_sdram_tmp <= '0';		
	end if;
end if;
end process;

process(clk)								-- Every image comes, reset the receiving buffers
begin
if rising_edge(clk) then
	if counter1=x"0004" then			-- Note vd lasting time
		reset_buf_tmp <= '1';
	else
		reset_buf_tmp <= '0';
	end if;
end if;
end process;

reset_fsm_sdram <= (reset_fsm_sdram_tmp or reset_tmp);
reset_buf <= (reset_buf_tmp or reset_tmp);

end Behavioral;