transmitter.vhd

编码器系统

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    16:16:54 12/02/2007 
-- Design Name: 
-- Module Name:    transmitter - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity transmitter is
port	(
			clk : in std_logic;
			reset : in std_logic;
			write : in  std_logic;
			data_in : in std_logic_vector(7 downto 0);
			ready : out std_logic;
			tx : out std_logic
		);
end transmitter;

architecture Behavioral of transmitter is

type state_type is (st_check, start_bit, q7, q6, q5, q4, q3, q2, q1, q0, stop_bit);
signal state : state_type := st_check;
signal q : std_logic_vector(7 downto 0) := (others=>'0');
signal counter : integer range 0 to 2603 := 0;		-- 19200 bps

begin

process(clk)
begin
if rising_edge(clk) then
	if reset='1' then
		state <= st_check;
	else
		case (state) is          
			when st_check =>
				if write='1' then
					state <= start_bit;
				end if;
				
			when start_bit =>
				if counter=2603 then
					state <= q7;
				end if;

			when q7 =>
				if counter=2603 then
					state <= q6;
				end if;

			when q6 =>
				if counter=2603 then
					state <= q5;
				end if;

			when q5 =>
				if counter=2603 then
					state <= q4;
				end if;

			when q4 =>
				if counter=2603 then
					state <= q3;
				end if;

			when q3 =>
				if counter=2603 then
					state <= q2;
				end if;

			when q2 =>
				if counter=2603 then
					state <= q1;
				end if;

			when q1 =>
				if counter=2603 then
					state <= q0;
				end if;

			when q0 =>
				if counter=2603 then
					state <= stop_bit;
				end if;

			when stop_bit =>
				if counter=2603 then
					state <= st_check;
				end if;
		end case;
	end if;
end if;
end process;

process(clk)
begin
if rising_edge(clk) then
	case (state) is
		when st_check =>
			tx <= '1';
			ready <= '1';
			
			if write='1' then				-- Data comming company with the write signal
				q <= data_in;
			end if;
		
		when start_bit =>
			tx <= '0';
			ready <= '0';
			
		when q7 =>
			tx <= q(7);
			ready <= '0';

		when q6 =>
			tx <= q(6);
			ready <= '0';

		when q5 =>
			tx <= q(5);
			ready <= '0';

		when q4 =>
			tx <= q(4);
			ready <= '0';

		when q3 =>
			tx <= q(3);
			ready <= '0';

		when q2 =>
			tx <= q(2);
			ready <= '0';

		when q1 =>
			tx <= q(1);
			ready <= '0';

		when q0 =>
			tx <= q(0);
			ready <= '0';

		when stop_bit =>
			tx <= '1';
			ready <= '0';
	end case;
end if;
end process;

process(clk)
begin
if rising_edge(clk) then
	if reset='1' then
		counter <= 0;
	elsif state=st_check then
		counter <= 0;
	elsif counter=2603 then
		counter <= 0;
	else
		counter <= counter + 1;
	end if;
end if;
end process;

end Behavioral;