ata_pio_access.vhd

编码器系统

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    10:26:38 07/23/2007 
-- Design Name: 
-- Module Name:    ATA_PIO_Access - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ata_pio_access is
port	(	
			clk : in std_logic;
			reset : in std_logic;
			addr : in std_logic_vector(4 downto 0);
			data_out : out std_logic_vector(15 downto 0);
			data_in : in std_logic_vector(15 downto 0);
			we : in std_logic;
			strb : in std_logic;
			dd_out : out std_logic_vector(15 downto 0);
			dd_in : in std_logic_vector(15 downto 0);
			da : out std_logic_vector(2 downto 0);
			cs0_n : out std_logic;
			cs1_n : out std_logic;
			dior_n : out std_logic;
			diow_n : out std_logic
		);
end ata_pio_access;

architecture Behavioral of ata_pio_access is
signal counter : std_logic_vector(2 downto 0);

begin
---------------------------------------------------------------------------------
----- Not using state machine for design because of its simple timing       -----
----- Since rising edge found strb='1', all signals must be valid in 6 clks -----
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process(clk)
begin
if rising_edge(clk) then
	if reset='1' then
		counter <= (others=>'0');
	elsif strb='1' then
		if counter="101" then
			counter <= (others=>'0');
		else
			counter <= counter + 1;
		end if;
	else
		counter <= (others=>'0');
	end if;
end if;
end process;

------------------------------
----- Address Part Logic -----
------------------------------
process(clk)
begin
if rising_edge(clk) then
	if reset='1' then
		cs1_n <= '1';
		cs0_n <= '1';
		da <= (others=>'0');
	elsif strb='1' then
		cs1_n <= addr(4);
		cs0_n <= addr(3);
		da <= addr(2 downto 0);
	end if;
end if;
end process;

--------------------------
----- ATA Data Logic -----
--------------------------
process(clk)
begin
if rising_edge(clk) then
	if reset='1' then
		dd_out <= (others=>'0');
	elsif strb='1' and we='1' then
		dd_out <= data_in;
	end if;
end if;
end process;

---------------------------
----- Host Data Logic -----
---------------------------
process(clk)
begin
if rising_edge(clk) then
	if reset='1' then
		data_out <= (others=>'0');
	elsif strb='1' and we='0' then
		data_out <= dd_in;
	end if;
end if;
end process;

-----------------------------
----- ATA Control Logic -----
-----------------------------
process(clk)
begin
if rising_edge(clk) then
	if reset='1' then
		dior_n <= '1';
	elsif (strb='1' and we='0' and (counter="001" or counter="010" or counter="011" or counter="100")) then
		dior_n <= '0';	
	else
		dior_n <= '1';
	end if;
end if;
end process;

process(clk)
begin
if rising_edge(clk) then
	if reset='1' then
		diow_n <= '1';
	elsif (strb='1' and we='1' and (counter="001" or counter="010" or counter="011" or counter="100")) then
		diow_n <= '0';	
	else
		diow_n <= '1';
	end if;
end if;
end process;

end Behavioral;