transmit_state.vhd

编码器系统

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    21:21:37 12/02/2007 
-- Design Name: 
-- Module Name:    transmit_state - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity transmit_state is
port	(
			clk : in std_logic;
			reset : in std_logic;
			ready : in std_logic;
			reg : in std_logic_vector(7 downto 0);
			write : out std_logic;
			data : out std_logic_vector(7 downto 0)
		);
end transmit_state;

architecture Behavioral of transmit_state is

type state_type is (st_idle, st_transmit_ee, st_transmit_16, st_transmit_data, st_transmit_crc);
signal state : state_type := st_idle;
signal counter_timer : std_logic_vector(17 downto 0) := (others=>'0');
signal counter : std_logic_vector(7 downto 0) := (others=>'0');
signal reg_crc : std_logic_vector(7 downto 0) := (others=>'0');
signal low_clk : std_logic := '0';

begin

process(low_clk)
begin
if rising_edge(low_clk) then
	if reset='1' then
		state <= st_idle;
	else
		case (state) is
			when st_idle =>
--				if counter_timer="101111101011110000" then		-- 1s
				if counter_timer="000000011111010000" then		-- 10ms
					state <= st_transmit_ee;
				end if;
				
			when st_transmit_ee =>
				if ready='1' then
					state <= st_transmit_16;
				end if;
				
			when st_transmit_16 =>
				if ready='1' then
					state <= st_transmit_data;
				end if;
				
			when st_transmit_data =>
				if ready='1' then
					state <= st_transmit_crc;
				end if;
				
			when st_transmit_crc =>
				if ready='1' then
					state <= st_idle;
				end if;
		end case;
	end if;
end if;
end process;

process(low_clk)
begin
if rising_edge(low_clk) then
	if reset='1' then
		write <= '0';
		data <= (others=>'0');
	else
		case (state) is
			when st_idle =>
				write <= '0';
				data <= (others=>'0');
			
			when st_transmit_ee =>
				if ready='1' then
					write <= '1';
					data <= x"EE";
				else
					write <= '0';
					data <= (others=>'0');
				end if;
				
			when st_transmit_16 =>
				if ready='1' then
					write <= '1';
					data <= x"16";
				else
					write <= '0';
					data <= (others=>'0');
				end if;
				
			when st_transmit_data =>
				if ready='1' then
					write <= '1';
					data <= reg;
				else
					write <= '0';
					data <= (others=>'0');
				end if;
				
			when st_transmit_crc =>
				if ready='1' then
					write <= '1';
					data <= reg_crc;
				else
					write <= '0';
					data <= (others=>'0');
				end if;
		end case;
	end if;
end if;
end process;

process(clk)
begin
if rising_edge(clk) then
	reg_crc <= x"04" + reg;
end if;
end process;

process(low_clk)
begin
if rising_edge(low_clk) then
	if reset='1' then
		counter_timer <= (others=>'0');
--	elsif counter_timer="101111101011110000" then		-- 1s
	elsif counter_timer="000000011111010000" then		-- 10ms
		counter_timer <= (others=>'0');
	else
		counter_timer <= counter_timer + 1;
	end if;
end if;
end process;

process(clk)
begin
if rising_edge(clk) then
	counter <= counter + 1;
end if;
end process;

low_clk <= counter(7);				-- 50MHz clk => 0.2MHz low_clk

end Behavioral;