receive_state.vhd

编码器系统

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    22:22:32 12/01/2007 
-- Design Name: 
-- Module Name:    receive_state - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity receive_state is
port	(
			clk16x : in std_logic;
			reset : in std_logic;
			read : in std_logic;
			data : in std_logic_vector(7 downto 0);
			addr_w : out std_logic_vector(4 downto 0)
		);
end receive_state;

architecture Behavioral of receive_state is

type state_type is (st_rx_ee, st_rx_16, st_rx_data, st_err);
signal state : state_type := st_rx_ee;
signal addr : std_logic_vector(4 downto 0) := (others=>'0');
signal counter_timeout : std_logic_vector(12 downto 0) := (others=>'0');

begin

process(clk16x)
begin
if rising_edge(clk16x) then
	if reset='1' then
		state <= st_rx_ee;
	else
		case (state) is
			when st_rx_ee =>
				if (read='1' and data=x"EE") then
					state <= st_rx_16;
				end if;
				
			when st_rx_16 =>
				if (read='1' and data=x"16") then
					state <= st_rx_data;
				elsif read='1' then
					state <= st_err;
				elsif counter_timeout="1011111110110" then		-- 20ms
	--			elsif counter_timeout="0000000010000" then		-- Simulation
					state <= st_err;
				end if;
				
			when st_rx_data =>
				if (read='1' and addr="11111") then
					state <= st_rx_ee;
				elsif counter_timeout="1011111110110" then
	--			elsif counter_timeout="0000000010000" then		-- Simulation
					state <= st_err;
				end if;
				
			when st_err =>
				state <= st_rx_ee;
		end case;
	end if;
end if;	
end process;

process(clk16x)
begin
if rising_edge(clk16x) then
	if reset='1' then
		addr <= (others=>'0');
	else
		case (state) is
			when st_rx_ee =>
				if (read='1' and data=x"EE") then
					addr <= addr + 1;
				end if;
				
			when st_rx_16 =>
				if (read='1' and data=x"16") then
					addr <= addr + 1;
				end if;
			
			when st_rx_data =>
				if read='1' then
				 addr <= addr + 1;
				end if;
					
			when st_err =>
				addr <= (others=>'0');
		end case;
	end if;
end if;
end process;

process(clk16x)
begin
if rising_edge(clk16x) then
	if reset='1' then
		counter_timeout <= (others=>'0');
	elsif read='1' then
		counter_timeout <= (others=>'0');
	else
		counter_timeout <= counter_timeout + 1;
	end if;
end if;
end process;

addr_w <= addr;

end Behavioral;