fifo2sd.xco

编码器系统

# BEGIN Project Options
SET flowvendor = Foundation_iSE
SET vhdlsim = True
SET verilogsim = True
SET workingdirectory = D:\Routine\ISE\ENCODE_SYSTEM
SET speedgrade = -4
SET simulationfiles = Behavioral
SET asysymbol = True
SET addpads = False
SET device = xc3s2000
SET implementationfiletype = Edif
SET busformat = BusFormatAngleBracketNotRipped
SET foundationsym = False
SET package = fg676
SET createndf = False
SET designentry = VHDL
SET devicefamily = spartan3
SET formalverification = False
SET removerpms = False
# END Project Options
# BEGIN Select
SELECT Fifo_Generator family Xilinx,_Inc. 3.2
# END Select
# BEGIN Parameters
CSET write_data_count=false
CSET almost_empty_flag=false
CSET full_threshold_negate_value=499
CSET empty_threshold_negate_value=3
CSET output_data_width=16
CSET input_depth=1024
CSET valid_flag=false
CSET programmable_empty_type=Single_Programmable_Empty_Threshold_Constant
CSET write_acknowledge_flag=false
CSET underflow_flag=false
CSET fifo_implementation=Independent_Clocks_Block_RAM
CSET use_extra_logic=false
CSET write_data_count_width=10
CSET valid_sense=Active_High
CSET data_count_width=10
CSET output_depth=1024
CSET dout_reset_value=0
CSET reset_pin=true
CSET underflow_sense=Active_High
CSET component_name=fifo2sd
CSET overflow_sense=Active_High
CSET overflow_flag=false
CSET read_data_count=false
CSET data_count=false
CSET programmable_full_type=Single_Programmable_Full_Threshold_Constant
CSET read_data_count_width=10
CSET reset_type=Asynchronous_Reset
CSET performance_options=Standard_FIFO
CSET full_threshold_assert_value=500
CSET almost_full_flag=false
CSET write_acknowledge_sense=Active_High
CSET read_clock_frequency=100
CSET empty_threshold_assert_value=2
CSET input_data_width=16
CSET write_clock_frequency=100
# END Parameters
GENERATE