ata_mux.vhd

编码器系统

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    15:02:53 11/15/2007 
-- Design Name: 
-- Module Name:    ata_mux - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ata_mux is
port	(
			dsp_awe_n : in std_logic;
			dsp_are_n : in std_logic;
			dsp_ce3_n : in std_logic;
			dsp_a : in std_logic_vector(6 downto 2);
			reg_3 : in std_logic_vector(31 downto 0);
			
			fpga_diow_n : in std_logic;
			fpga_dior_n : in std_logic;
			fpga_da : in std_logic_vector(2 downto 0);
			fpga_cs1_n : in std_logic;
			fpga_cs0_n : in std_logic;
			
			diow_n : out std_logic;
			dior_n : out std_logic;
			da : out std_logic_vector(2 downto 0);
			cs1_n : out std_logic;
			cs0_n : out std_logic
		);			
end ata_mux;

architecture Behavioral of ata_mux is

begin

diow_n <= dsp_awe_n when (reg_3=x"00000000" and  dsp_ce3_n='0') else
			fpga_diow_n when (reg_3=x"00000055") else '1';

dior_n <= dsp_are_n when (reg_3=x"00000000" and dsp_ce3_n='0') else 
			fpga_dior_n when (reg_3=x"00000055") else '1';
		
da <= dsp_a(4 downto 2) when (reg_3=x"00000000" and dsp_ce3_n='0') else
		fpga_da when (reg_3=x"00000055") else (others=>'1');
		
cs1_n <= dsp_a(6) when (reg_3=x"00000000" and dsp_ce3_n='0') else
			fpga_cs1_n when (reg_3=x"00000055") else '1';
				
cs0_n <= dsp_a(5) when (reg_3=x"00000000" and dsp_ce3_n='0') else 
			fpga_cs0_n when (reg_3=x"00000055") else '1';

end Behavioral;