system_top.vhd

编码器系统

end component;

component interface_422 is
port	(
			clk : in std_logic;
			reset: in std_logic;
			data_out : out std_logic;
			dsp_ce0_n : in std_logic;
			dsp_awe_n : in std_logic;
			dsp_aoe_n : in std_logic;
			dsp_a : in std_logic_vector(21 downto 2);
			reg_0 : in std_logic_vector(31 downto 0);
			reg_1 : in std_logic_vector(31 downto 0);
			reg_2 : out std_logic_vector(31 downto 0);
			sram_ce1_n : out std_logic;
			sram_ce2 : out std_logic;
			sram_we_n : out std_logic;
			sram_oe_n : out std_logic;
			sram_addr : out std_logic_vector(19 downto 0);
			sram_addr20 : out std_logic;
			sram_d_in : in std_logic_vector(7 downto 0)
		);
end component;

component comm_top is
port	(
			clk : in std_logic;
			reset : in std_logic;
			rx : in std_logic;
			dsp_are_n : in std_logic;
			addr_r : in std_logic_vector(4 downto 0);
			data_out : out std_logic_vector(7 downto 0);
			reg : in std_logic_vector(7 downto 0);          
			tx : out std_logic
		);
end component;

signal reg_0 : std_logic_vector(31 downto 0) := (others=>'0');
signal reg_1 : std_logic_vector(31 downto 0) := (others=>'0');
signal reg_2 : std_logic_vector(31 downto 0) := (others=>'0');
signal reg_3 : std_logic_vector(31 downto 0) := (others=>'0');
signal reg_4 : std_logic_vector(31 downto 0) := (others=>'0');
signal reg_5 : std_logic_vector(31 downto 0) := (others=>'0');
signal reg_6 : std_logic_vector(31 downto 0) := (others=>'0');
signal reg_8 : std_logic_vector(31 downto 0) := (others=>'0');

signal vd : std_logic := '0';
signal reset : std_logic := '0';
signal reset_fsm_sdram : std_logic := '0';
signal start_ata : std_logic := '0';
signal ata_irq : std_logic := '0';		

signal reset_data_src : std_logic := '0';
signal reset_buf : std_logic := '0';
signal ccd_clk : std_logic := '0';
signal ccd_data_in : std_logic_vector(15 downto 0) := (others=>'0');

signal fifo2sd_din : std_logic_vector(15 downto 0) := (others=>'0');
signal fifo2sd_wr_en : std_logic := '0';
signal fifo2sd_rd_en : std_logic := '0';
signal fifo2sd_full : std_logic := '0';

signal sd2fifo_en : std_logic := '0';
signal sd2fifo_empty : std_logic := '0';
signal sd2fifo_full : std_logic := '0';

signal fifo2ata_en : std_logic := '0';
signal fifo2ata_clk : std_logic := '0';
signal fifo2ata_d : std_logic_vector(15 downto 0) := (others=>'0');

signal dsp_d_in : std_logic_vector(31 downto 0) := (others=>'0');

signal sd_dq_in : std_logic_vector(15 downto 0) := (others=>'0');
signal sd_dq_out : std_logic_vector(15 downto 0) := (others=>'0');
signal sd_dq_tri : std_logic := '0';
signal sd_ck_tmp : std_logic := '0';

signal dd_in : std_logic_vector(15 downto 0) := (others=>'0');
signal fpga_dd_out : std_logic_vector(15 downto 0) := (others=>'0');
signal dd_tri : std_logic := '0';

signal fpga_diow_n : std_logic := '0';
signal fpga_dior_n : std_logic := '0';
signal fpga_da : std_logic_vector(2 downto 0) := (others=>'0');
signal fpga_cs1_n : std_logic := '0';
signal fpga_cs0_n : std_logic := '0';

signal sram_d_in : std_logic_vector(7 downto 0) := (others=>'0');

signal data_out_param : std_logic_vector(7 downto 0) := (others=>'0');

begin

inst_system_reg : system_reg
port map	(	
				clk => clk,
				reset => reset,
				dsp_a => dsp_a,
				dsp_ce0_n => dsp_ce0_n,
				dsp_awe_n => dsp_awe_n,
				dsp_d_in => dsp_d_in,
				
				reg_0 => reg_0,
				reg_1 => reg_1,
				reg_3 => reg_3,
				reg_4 => reg_4,
				reg_5 => reg_5,
				reg_6 => reg_6,
				reg_8 => reg_8
			);

inst_system_tri_io : system_tri_io
port map	(
				dsp_a => dsp_a,
				dsp_d => dsp_d,
				dsp_d_in => dsp_d_in,
				dsp_ce0_n => dsp_ce0_n,
				dsp_ce3_n => dsp_ce3_n,
				dsp_aoe_n => dsp_aoe_n,
							
				sd_dq => sd_dq,
				sd_dq_in => sd_dq_in,
				sd_dq_out => sd_dq_out,
				sd_dq_tri => sd_dq_tri,
				
				dd => dd,
				dd_in => dd_in,
				fpga_dd_out => fpga_dd_out,
				reg_3 => reg_3,
				dd_tri => dd_tri,
							
				sram_d => sram_d,
				sram_d_in => sram_d_in,
				reg_2 => reg_2,
				
				data_out_param => data_out_param
			);

inst_dsp_peri : dsp_peri
port map	(
				fpga_clk_50m => clk,
				reset => reset,
				ata_irq => ata_irq,
				
				dsp_a => dsp_a(21 downto 6),
				dsp_ce0_n => dsp_ce0_n,
				dsp_ce1_n => dsp_ce1_n,
				dsp_ce2_n => dsp_ce2_n,
				dsp_aoe_n => dsp_aoe_n,
				dsp_awe_n => dsp_awe_n,
				dsp_gpio_0 => dsp_gpio_0,
				dsp_gpio_1 => dsp_gpio_1,
				dsp_gpio_2 => dsp_gpio_2,
				dsp_gpio_6 => dsp_gpio_6,
				dsp_gpio_7 => dsp_gpio_7,
				dsp_int0_n => dsp_int0_n,
				dsp_int1_n => dsp_int1_n,
				dsp_int2_n => dsp_int2_n,
				dsp_int3_n => dsp_int3_n,
				dsp_nmi_n => dsp_nmi_n,
				dsp_reset_n => dsp_reset_n,
				dsp_ardy => dsp_ardy,
				dsp_hcs_n => dsp_hcs_n,
				dsp_hold_n => dsp_hold_n,
				
				flash_rst_n => flash_rst_n,
				flash_ce_n => flash_ce_n,
				flash_oe_n => flash_oe_n,
				flash_we_n => flash_we_n,
				flash_wp_n => flash_wp_n,
				
				sram_hce1_n => sram_hce1_n,
				sram_hce2 => sram_hce2,
				sram_hoe_n => sram_hoe_n,
				sram_hwe_n => sram_hwe_n,
				sram_hble_n => sram_hble_n,
				sram_hbhe_n => sram_hbhe_n,
				sram_lce1_n => sram_lce1_n,
				sram_lce2 => sram_lce2,
				sram_loe_n => sram_loe_n,
				sram_lwe_n => sram_lwe_n,
				sram_lble_n => sram_lble_n,
				sram_lbhe_n => sram_lbhe_n,
				
				adv202_reset_n => adv202_reset_n,
				adv202_cs_n => adv202_cs_n,
				adv202_wr_n => adv202_wr_n,
				adv202_rd_n => adv202_rd_n,
				adv202_dack0_n => adv202_dack0_n,
				adv202_dack1_n => adv202_dack1_n,
				adv202_irq_n => adv202_irq_n,
				adv202_clk => adv202_clk
			);

inst_syscon : syscon
port map	(
				clk => clk,
				vd => vd,
				reg_5 => reg_5,
				reg_6 => reg_6,
				
				reset => reset,
				ata_reset_n => ata_reset_n,
				start_ata => start_ata,

				reset_data_src => reset_data_src,
				reset_buf => reset_buf,
				reset_fsm_sdram => reset_fsm_sdram
			);
			
inst_data_src : data_src
port map	(		
				reset => reset_data_src,
				clk => clk,
				vd => vd,
				ccd_clk => ccd_clk,
				ccd_data_in => ccd_data_in
			);
			
inst_ping_pong_buffer : ping_pong_buffer
port map	(
				reset => reset_buf,
				reg_4 => reg_4,
				clka => ccd_clk,
				clkb => clk,
				dina => ccd_data_in,
				doutb => fifo2sd_din,
				oe => fifo2sd_wr_en
			);
			
inst_fifo2sd : fifo2sd
port map	(	
				din => fifo2sd_din,
				rd_clk => clk,
				rd_en => fifo2sd_rd_en,
				rst => reset_buf,
				wr_clk => clk,
				wr_en => fifo2sd_wr_en,
				dout => sd_dq_out,
				empty => open,
				full => open,
				prog_empty => open,
				prog_full => fifo2sd_full
			);
			
inst_fsm_sdram : fsm_sdram
port map	(	
				sys_clk => clk,
				sys_rst => reset_fsm_sdram,
				sys_start => reset_buf,
				
				fifo2sd_full => fifo2sd_full,
				fifo2sd_en => fifo2sd_rd_en,
				sd2fifo_empty => sd2fifo_empty,
				sd2fifo_en => sd2fifo_en,
				
				dq_tri_en => sd_dq_tri,
				sd_cke => sd_cke,
				sd_ck => sd_ck_tmp,
				sd_cs_n => sd_cs_n,
				sd_ras_n => sd_ras_n,
				sd_cas_n => sd_cas_n,
				sd_we_n => sd_we_n,
				sd_dqm => sd_dqm,
				sd_ba => sd_ba,
				sd_a => sd_a
			);

sd_ck <= sd_ck_tmp;
			
inst_sd2fifo : sd2fifo
port map	(
				din => sd_dq_in,
				rd_clk => fifo2ata_clk,
				rd_en => fifo2ata_en,
				rst => reset,
				wr_clk => sd_ck_tmp,
				wr_en => sd2fifo_en,
				dout => fifo2ata_d,
				empty => open,
				full => open,
				prog_empty => sd2fifo_empty,
				prog_full => sd2fifo_full
			);
			
inst_ata_ctrl : ata_ctrl
port map	(	
				-- SYSCON signals
				clk => clk,
				reset => reset,
				start_ata => start_ata,
				data_rdy => sd2fifo_full,
				ata_irq => ata_irq,
				
				-- DSP signals
				dsp_ce0_n => dsp_ce0_n,
				dsp_awe_n => dsp_awe_n,
				dsp_a => dsp_a,
				dsp_d_in => dsp_d_in,
				
				-- CTRL module data access signals
				fifo2ata => fifo2ata_d,
				fifo2ata_clk => fifo2ata_clk,
				fifo2ata_en => fifo2ata_en,
				
				-- ATA interface signals
				dd_out => fpga_dd_out,
				dd_in => dd_in,
				da => fpga_da,
				cs0_n => fpga_cs0_n,
				cs1_n => fpga_cs1_n,
				dior_n => fpga_dior_n,
				diow_n => fpga_diow_n,
				dmack_n => dmack_n,
				dd_out_en => dd_tri
			);
			
inst_ata_mux : ata_mux
port map	(
				dsp_awe_n => dsp_awe_n,
				dsp_are_n => dsp_are_n,
				dsp_ce3_n => dsp_ce3_n,
				dsp_a => dsp_a(6 downto 2),
				reg_3 => reg_3,
				
				fpga_diow_n => fpga_diow_n,
				fpga_dior_n => fpga_dior_n,
				fpga_da => fpga_da,
				fpga_cs1_n => fpga_cs1_n,
				fpga_cs0_n => fpga_cs0_n,
				
				diow_n => diow_n,
				dior_n => dior_n,
				da => da,
				cs1_n => cs1_n,
				cs0_n => cs0_n
			);

inst_interface_422 : interface_422
port map	(
				clk => clk,
				reset => reset,
				data_out => data_out_422,
				dsp_ce0_n => dsp_ce0_n,
				dsp_awe_n => dsp_awe_n,
				dsp_aoe_n => dsp_aoe_n,
				dsp_a => dsp_a,
				reg_0 => reg_0,
				reg_1 => reg_1,
				reg_2 => reg_2,
				sram_ce1_n => sram_ce1_n,
				sram_ce2 => sram_ce2,
				sram_we_n => sram_we_n,
				sram_oe_n => sram_oe_n,
				sram_addr => sram_addr,
				sram_addr20 => sram_addr20,
				sram_d_in => sram_d_in
			);
			
inst_comm_top : comm_top
port map	(
				clk => clk,
				reset => reset,
				rx => rx,
				dsp_are_n => dsp_are_n,
				addr_r => dsp_a(6 downto 2),
				data_out => data_out_param,
				reg => reg_8(7 downto 0),
				tx => tx
			);

end Behavioral;