system_top.vhd

编码器系统

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    15:17:08 07/04/2007 
-- Design Name: 
-- Module Name:    system_top - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity system_top is
port	(
			clk : in std_logic;
			
			data_out_422 : out std_logic;
			rx : in std_logic;
			tx : out std_logic;

			dsp_d : inout std_logic_vector(31 downto 0);
			dsp_a : in std_logic_vector(21 downto 2);
			dsp_ce0_n : in std_logic;
			dsp_ce1_n : in std_logic;
			dsp_ce2_n : in std_logic;
			dsp_ce3_n : in std_logic;
			dsp_aoe_n : in std_logic;
			dsp_awe_n : in std_logic;
			dsp_are_n : in std_logic;
			dsp_gpio_0 : out std_logic;
			dsp_gpio_1 : out std_logic;
			dsp_gpio_2 : out std_logic;
			dsp_gpio_6 : out std_logic;
			dsp_gpio_7 : out std_logic;
			dsp_int0_n : out std_logic;
			dsp_int1_n : out std_logic;
			dsp_int2_n : out std_logic;
			dsp_int3_n : out std_logic;
			dsp_nmi_n : out std_logic;
			dsp_reset_n : out std_logic;
			dsp_ardy : out std_logic;
			dsp_hcs_n : out std_logic;
			dsp_hold_n : out std_logic;
		
			flash_rst_n : out std_logic;
			flash_ce_n : out std_logic;
			flash_oe_n : out std_logic;
			flash_we_n : out std_logic;
			flash_wp_n : out std_logic;
		
			sram_hce1_n : out std_logic;
			sram_hce2 : out std_logic;
			sram_hoe_n : out std_logic;
			sram_hwe_n : out std_logic;
			sram_hble_n : out std_logic;
			sram_hbhe_n : out std_logic;
		
			sram_lce1_n : out std_logic;
			sram_lce2 : out std_logic;
			sram_loe_n : out std_logic;
			sram_lwe_n : out std_logic;
			sram_lble_n : out std_logic;
			sram_lbhe_n : out std_logic;
		
			adv202_reset_n : out std_logic;
			adv202_cs_n : out std_logic;
			adv202_wr_n : out std_logic;
			adv202_rd_n : out std_logic;
			adv202_dack0_n : out std_logic;
			adv202_dack1_n : out std_logic;
			adv202_irq_n : in std_logic;
			adv202_clk : out std_logic;
			
			sd_dq : inout std_logic_vector(15 downto 0);			
			sd_cke : out std_logic;
			sd_ck : out std_logic;
			sd_cs_n : out std_logic;
			sd_ras_n : out std_logic;
			sd_cas_n : out std_logic;
			sd_we_n : out std_logic;
			sd_dqm : out std_logic_vector(1 downto 0);
			sd_ba : out std_logic_vector(1 downto 0);
			sd_a : out std_logic_vector(12 downto 0);
			
			ata_reset_n : out std_logic;
			dd : inout std_logic_vector(15 downto 0);
			da : out std_logic_vector(2 downto 0);
			cs0_n : out std_logic;
			cs1_n : out std_logic;
			dior_n : out std_logic;
			diow_n : out std_logic;
			dmack_n : out std_logic;
			
			sram_ce1_n : out std_logic;
			sram_ce2 : out std_logic;
			sram_we_n : out std_logic;
			sram_oe_n : out std_logic;
			sram_addr : out std_logic_vector(19 downto 0);
			sram_addr20 : out std_logic;
			sram_d : inout std_logic_vector(7 downto 0)
		);
end system_top;

architecture Behavioral of system_top is

component system_reg is
port	(	
			clk : in std_logic;
			reset : in std_logic;
			dsp_a : in std_logic_vector(21 downto 2);
			dsp_ce0_n : in std_logic;
			dsp_awe_n : in std_logic;
			dsp_d_in : in std_logic_vector(31 downto 0);
			
			reg_0 : out std_logic_vector(31 downto 0);
			reg_1 : out std_logic_vector(31 downto 0);
			reg_3 : out std_logic_vector(31 downto 0);
			reg_4 : out std_logic_vector(31 downto 0);
			reg_5 : out std_logic_vector(31 downto 0);
			reg_6 : out std_logic_vector(31 downto 0);
			reg_8 : out std_logic_vector(31 downto 0)
		);
end component;

component system_tri_io is
port	(
			dsp_a : in std_logic_vector(21 downto 2);
			dsp_d : inout std_logic_vector(31 downto 0);
			dsp_d_in : out std_logic_vector(31 downto 0);
			dsp_ce0_n : in std_logic;
			dsp_ce3_n : in std_logic;
			dsp_aoe_n : in std_logic;
						
			sd_dq : inout std_logic_vector(15 downto 0);
			sd_dq_in : out std_logic_vector(15 downto 0);
			sd_dq_out : in std_logic_vector(15 downto 0);
			sd_dq_tri : in std_logic;
			
			dd : inout std_logic_vector(15 downto 0);
			dd_in : out std_logic_vector(15 downto 0);
			fpga_dd_out : in std_logic_vector(15 downto 0);
			reg_3 : in std_logic_vector(31 downto 0);
			dd_tri : in std_logic;
			
			sram_d : inout std_logic_vector(7 downto 0);
			sram_d_in : out std_logic_vector(7 downto 0);
			reg_2 : in std_logic_vector(31 downto 0);
			
			data_out_param : in std_logic_vector(7 downto 0)
		);			
end component;

component dsp_peri is
port	(
			fpga_clk_50m : in std_logic;
			reset : in std_logic;
			ata_irq : in std_logic;

			dsp_a : in std_logic_vector(21 downto 6);
			dsp_ce0_n : in std_logic;
			dsp_ce1_n : in std_logic;
			dsp_ce2_n : in std_logic;
			dsp_aoe_n : in std_logic;
			dsp_awe_n : in std_logic;
			dsp_gpio_0 : out std_logic;
			dsp_gpio_1 : out std_logic;
			dsp_gpio_2 : out std_logic;
			dsp_gpio_6 : out std_logic;
			dsp_gpio_7 : out std_logic;
			dsp_int0_n : out std_logic;
			dsp_int1_n : out std_logic;
			dsp_int2_n : out std_logic;
			dsp_int3_n : out std_logic;
			dsp_nmi_n : out std_logic;
			dsp_reset_n : out std_logic;
			dsp_ardy : out std_logic;
			dsp_hcs_n : out std_logic;
			dsp_hold_n : out std_logic;
		
			flash_rst_n : out std_logic;
			flash_ce_n : out std_logic;
			flash_oe_n : out std_logic;
			flash_we_n : out std_logic;
			flash_wp_n : out std_logic;
		
			sram_hce1_n : out std_logic;
			sram_hce2 : out std_logic;
			sram_hoe_n : out std_logic;
			sram_hwe_n : out std_logic;
			sram_hble_n : out std_logic;
			sram_hbhe_n : out std_logic;
		
			sram_lce1_n : out std_logic;
			sram_lce2 : out std_logic;
			sram_loe_n : out std_logic;
			sram_lwe_n : out std_logic;
			sram_lble_n : out std_logic;
			sram_lbhe_n : out std_logic;
		
			adv202_reset_n : out std_logic;
			adv202_cs_n : out std_logic;
			adv202_wr_n : out std_logic;
			adv202_rd_n : out std_logic;
			adv202_dack0_n : out std_logic;
			adv202_dack1_n : out std_logic;
			adv202_irq_n : in std_logic;
			adv202_clk : out std_logic
		);
end component;

component syscon is
port	(	
			clk : in std_logic;
			vd : in std_logic;
			reg_5 : in std_logic_vector(31 downto 0);
			reg_6 : in std_logic_vector(31 downto 0);
			
			reset : out std_logic;
			ata_reset_n : out std_logic;
			start_ata : out std_logic;

			reset_data_src : out std_logic;
			reset_buf : out std_logic;
			reset_fsm_sdram : out std_logic
		);
end component;

component data_src is
port	(
			reset : in std_logic;
			clk : in std_logic;
			vd : out std_logic;
			ccd_clk : out std_logic;
			ccd_data_in : out std_logic_vector(15 downto 0)
		);
end component;

component ping_pong_buffer is
port	(
			reset : in std_logic;
			reg_4 : in std_logic_vector(31 downto 0);
			clka : in std_logic;
			clkb : in std_logic;			
			dina : in std_logic_vector(15 downto 0);
			doutb : out std_logic_vector(15 downto 0);
			oe : out std_logic
		);
end component;

component fifo2sd
port	(	
			din : in std_logic_vector(15 downto 0);
			rd_clk : in std_logic;
			rd_en : in std_logic;
			rst : in std_logic;
			wr_clk : in std_logic;
			wr_en : in std_logic;
			dout : out std_logic_vector(15 downto 0);
			empty : out std_logic;
			full : out std_logic;
			prog_empty : out std_logic;
			prog_full : out std_logic
		);
end component;

component fsm_sdram is
port	(	
			sys_clk : in std_logic;
			sys_rst : in std_logic;
			sys_start : in std_logic;
			
			fifo2sd_full : in std_logic;
			fifo2sd_en : out std_logic;
			sd2fifo_empty : in std_logic;
			sd2fifo_en : out std_logic;
			
			dq_tri_en : out std_logic;
			sd_cke : out std_logic;
			sd_ck : out std_logic;
			sd_cs_n : out std_logic;
			sd_ras_n : out std_logic;
			sd_cas_n : out std_logic;
			sd_we_n : out std_logic;
			sd_dqm : out std_logic_vector(1 downto 0);
			sd_ba : out std_logic_vector(1 downto 0);
			sd_a : out std_logic_vector(12 downto 0)
		);
end component;

component sd2fifo is
port	(
			din : in std_logic_vector(15 downto 0);
			rd_clk : in std_logic;
			rd_en : in std_logic;
			rst : in std_logic;
			wr_clk : in std_logic;
			wr_en : in std_logic;
			dout : out std_logic_vector(15 downto 0);
			empty : out std_logic;
			full : out std_logic;
			prog_empty : out std_logic;
			prog_full : out std_logic
		);
end component;

component ata_ctrl is
port	(	
			-- SYSCON signals
			clk : in std_logic;
			reset : in std_logic;
			start_ata : in std_logic;
			data_rdy : in std_logic;
			ata_irq : out std_logic;
			
			-- DSP signals
			dsp_ce0_n : in std_logic;
			dsp_awe_n : in std_logic;
			dsp_a : in std_logic_vector(21 downto 2);
			dsp_d_in : in std_logic_vector(31 downto 0);
			
			-- CTRL module data access signals
			fifo2ata : in std_logic_vector(15 downto 0);
			fifo2ata_clk : out std_logic;
			fifo2ata_en : out std_logic;
			
			-- ATA interface signals
			dd_out : out std_logic_vector(15 downto 0);
			dd_in : in std_logic_vector(15 downto 0);
			da : out std_logic_vector(2 downto 0);
			cs0_n : out std_logic;
			cs1_n : out std_logic;
			dior_n : out std_logic;
			diow_n : out std_logic;
			dmack_n :out std_logic;
			dd_out_en : out std_logic
		);
end component;

component ata_mux is
port	(
			dsp_awe_n : in std_logic;
			dsp_are_n : in std_logic;
			dsp_ce3_n : in std_logic;
			dsp_a : in std_logic_vector(6 downto 2);
			reg_3 : in std_logic_vector(31 downto 0);
			
			fpga_diow_n : in std_logic;
			fpga_dior_n : in std_logic;
			fpga_da : in std_logic_vector(2 downto 0);
			fpga_cs1_n : in std_logic;
			fpga_cs0_n : in std_logic;
			
			diow_n : out std_logic;
			dior_n : out std_logic;
			da : out std_logic_vector(2 downto 0);
			cs1_n : out std_logic;
			cs0_n : out std_logic
		);