coregen.xml

编码器系统

<?xml version="1.0" encoding="UTF-8"?>
<RootFolder label="COREGEN" treetype="folder" language="COREGEN">
	<Folder label="VERILOG Component Instantiation" treetype="folder">
		<Template label="dpram_rx" treetype="template">
 
 
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
 
dpram_rx YourInstanceName (
    .addra(addra),
    .addrb(addrb),
    .clka(clka),
    .clkb(clkb),
    .dina(dina),
    .doutb(doutb),
    .wea(wea));

 
		</Template>
		<Template label="fifo2sd" treetype="template">
 
 
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
 
fifo2sd YourInstanceName (
    .din(din),
    .rd_clk(rd_clk),
    .rd_en(rd_en),
    .rst(rst),
    .wr_clk(wr_clk),
    .wr_en(wr_en),
    .dout(dout),
    .empty(empty),
    .full(full),
    .prog_empty(prog_empty),
    .prog_full(prog_full));

 
		</Template>
		<Template label="sd2fifo" treetype="template">
 
 
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
 
sd2fifo YourInstanceName (
    .din(din),
    .rd_clk(rd_clk),
    .rd_en(rd_en),
    .rst(rst),
    .wr_clk(wr_clk),
    .wr_en(wr_en),
    .dout(dout),
    .empty(empty),
    .full(full),
    .prog_empty(prog_empty),
    .prog_full(prog_full));

 
		</Template>
	</Folder>
	<Folder label="VHDL Component Instantiation" treetype="folder">
		<Template label="dpram_rx" treetype="template">
 
 
-- The following code must appear in the VHDL architecture header:
 
component dpram_rx
    port (
    addra: IN std_logic_VECTOR(4 downto 0);
    addrb: IN std_logic_VECTOR(4 downto 0);
    clka: IN std_logic;
    clkb: IN std_logic;
    dina: IN std_logic_VECTOR(7 downto 0);
    doutb: OUT std_logic_VECTOR(7 downto 0);
    wea: IN std_logic);
end component;



 
-------------------------------------------------------------
 
-- The following code must appear in the VHDL architecture body.
-- Substitute your own instance name and net names.
 
your_instance_name : dpram_rx
        port map (
            addra =&gt; addra,
            addrb =&gt; addrb,
            clka =&gt; clka,
            clkb =&gt; clkb,
            dina =&gt; dina,
            doutb =&gt; doutb,
            wea =&gt; wea);
 
		</Template>
		<Template label="fifo2sd" treetype="template">
 
 
-- The following code must appear in the VHDL architecture header:
 
component fifo2sd
    port (
    din: IN std_logic_VECTOR(15 downto 0);
    rd_clk: IN std_logic;
    rd_en: IN std_logic;
    rst: IN std_logic;
    wr_clk: IN std_logic;
    wr_en: IN std_logic;
    dout: OUT std_logic_VECTOR(15 downto 0);
    empty: OUT std_logic;
    full: OUT std_logic;
    prog_empty: OUT std_logic;
    prog_full: OUT std_logic);
end component;



 
-------------------------------------------------------------
 
-- The following code must appear in the VHDL architecture body.
-- Substitute your own instance name and net names.
 
your_instance_name : fifo2sd
        port map (
            din =&gt; din,
            rd_clk =&gt; rd_clk,
            rd_en =&gt; rd_en,
            rst =&gt; rst,
            wr_clk =&gt; wr_clk,
            wr_en =&gt; wr_en,
            dout =&gt; dout,
            empty =&gt; empty,
            full =&gt; full,
            prog_empty =&gt; prog_empty,
            prog_full =&gt; prog_full);
 
		</Template>
		<Template label="sd2fifo" treetype="template">
 
 
-- The following code must appear in the VHDL architecture header:
 
component sd2fifo
    port (
    din: IN std_logic_VECTOR(15 downto 0);
    rd_clk: IN std_logic;
    rd_en: IN std_logic;
    rst: IN std_logic;
    wr_clk: IN std_logic;
    wr_en: IN std_logic;
    dout: OUT std_logic_VECTOR(15 downto 0);
    empty: OUT std_logic;
    full: OUT std_logic;
    prog_empty: OUT std_logic;
    prog_full: OUT std_logic);
end component;



 
-------------------------------------------------------------
 
-- The following code must appear in the VHDL architecture body.
-- Substitute your own instance name and net names.
 
your_instance_name : sd2fifo
        port map (
            din =&gt; din,
            rd_clk =&gt; rd_clk,
            rd_en =&gt; rd_en,
            rst =&gt; rst,
            wr_clk =&gt; wr_clk,
            wr_en =&gt; wr_en,
            dout =&gt; dout,
            empty =&gt; empty,
            full =&gt; full,
            prog_empty =&gt; prog_empty,
            prog_full =&gt; prog_full);
 
		</Template>
	</Folder>
</RootFolder>