system_reg.vhd

编码器系统

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    20:51:17 11/13/2007 
-- Design Name: 
-- Module Name:    system_reg - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity system_reg is
port	(	
			clk : in std_logic;
			reset : in std_logic;
			dsp_a : in std_logic_vector(21 downto 2);
			dsp_ce0_n : in std_logic;
			dsp_awe_n : in std_logic;
			dsp_d_in : in std_logic_vector(31 downto 0);
			
			reg_0 : out std_logic_vector(31 downto 0);
			reg_1 : out std_logic_vector(31 downto 0);
			reg_3 : out std_logic_vector(31 downto 0);
			reg_4 : out std_logic_vector(31 downto 0);
			reg_5 : out std_logic_vector(31 downto 0);
			reg_6 : out std_logic_vector(31 downto 0);
			reg_8 : out std_logic_vector(31 downto 0)
		);
end system_reg;

architecture Behavioral of system_reg is

begin

-- 422 state change
process(clk)
begin
if rising_edge(clk) then
	if reset='1' then
		reg_0 <= (others=>'0');
	elsif (dsp_ce0_n='0' and dsp_a=x"04010" and dsp_awe_n='0') then
		reg_0 <= dsp_d_in;
	end if;
end if;
end process;

-- 422 data number
process(clk)
begin
if rising_edge(clk) then
	if reset='1' then
		reg_1 <= (others=>'0');
	elsif (dsp_ce0_n='0' and dsp_a=x"04011" and dsp_awe_n='0') then
		reg_1 <= dsp_d_in;
	end if;
end if;
end process;

-- REG_2 is 422 state indicator

-- ATA switch
process(clk)
begin
if rising_edge(clk) then
	if reset='1' then
		reg_3 <= (others=>'0');
	elsif (dsp_ce0_n='0' and dsp_a=x"04013" and dsp_awe_n='0') then
		reg_3 <= dsp_d_in;
	end if;
end if;
end process;

-- Data switch
process(clk)
begin
if rising_edge(clk) then
	if reset='1' then
		reg_4 <= (others=>'0');
	elsif (dsp_ce0_n='0' and dsp_a=x"04014" and dsp_awe_n='0') then
		reg_4 <= dsp_d_in;
	end if;
end if;
end process;

-- Data source reset
process(clk)
begin
if rising_edge(clk) then
	if (dsp_ce0_n='0' and dsp_a=x"04015" and dsp_awe_n='0') then
		reg_5 <= dsp_d_in;
	end if;
end if;
end process;

-- System reset
process(clk)
begin
if rising_edge(clk) then
	if (dsp_ce0_n='0' and dsp_a=x"04016" and dsp_awe_n='0') then
		reg_6 <= dsp_d_in;
	end if;
end if;
end process;

-- REG_7 is LBA Address

-- Communication Byte
process(clk)
begin
if rising_edge(clk) then
	if reset='1' then
		reg_8 <= (others=>'0');
	elsif (dsp_ce0_n='0' and dsp_a=x"04018" and dsp_awe_n='0') then
		reg_8 <= dsp_d_in;
	end if;
end if;
end process;

end Behavioral;