ping_pong_buffer.vhd

编码器系统

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    14:31:04 07/06/2007 
-- Design Name: 
-- Module Name:    ping_pong_buffer - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ping_pong_buffer is
port	(
			reset : in std_logic;
			reg_4 : in std_logic_vector(31 downto 0);
			clka : in std_logic;
			clkb : in std_logic;			
			dina : in std_logic_vector(15 downto 0);
			doutb : out std_logic_vector(15 downto 0);
			oe : out std_logic
		);
end ping_pong_buffer;

architecture Behavioral of ping_pong_buffer is

type ram_type is array (0 to 2047) of std_logic_vector(15 downto 0);
signal dpram : ram_type;

signal addra, addrb : std_logic_vector(10 downto 0) := (others=>'0');
signal up_full, down_full : std_logic := '0';

begin


-----------------------------------------------------------------------------------
-----								Ping Pong Block Ram											-----
-----------------------------------------------------------------------------------
process(clka)
begin
if rising_edge(clka) then
	dpram(conv_integer(addra)) <= dina;
end if;
end process;

process(clkb)
begin
if rising_edge(clkb) then
	doutb <= dpram(conv_integer(addrb));
end if;
end process;

-----------------------------------------------------------------------------------
-----								Ping Pong Operation											-----
-----------------------------------------------------------------------------------

---------------------
-- Input Operation --
---------------------

process(reset, reg_4, clka)
begin
if (reset='1' or reg_4=x"00000000") then
	addra <= (others=>'0');
elsif rising_edge(clka) then				-- Storage is 2028 16-bit word
	if addra="11111101011" then
		addra <= (others=>'0');
	else
		addra <= addra + 1;
	end if;
end if;
end process;

---------------------
-- Operation Flags --
---------------------

process(reset, clka)
begin
if reset='1' then
	up_full <= '0';
	down_full <= '0';
elsif rising_edge(clka) then
	if addra="01111110101"  then			-- Half page 1014 16-bit word
		up_full <= '1';
		down_full <= '0';
	elsif addra="11111101011" then		-- Full page 2028 16-bit word
		up_full <= '0';
		down_full <= '1';
	end if;
end if;
end process;

----------------------
-- Output Operation --
----------------------

process(reset, clkb)
begin
if reset='1' then
	addrb <= (others=>'0');
	oe <= '0';
elsif rising_edge(clkb) then
	if up_full='1' then
		if addrb="01111110110" then		-- Half page 1014 16-bit word
			addrb <= addrb;
			oe <= '0';
		else
			addrb <= addrb + 1;
			oe <= '1';
		end if;
	elsif down_full='1' then
		if (addrb="11111101100" or addrb="00000000000") then		-- Full page 2028 16-bit word
			addrb <= (others=>'0');
			oe <= '0';
		else
			addrb <= addrb + 1;
			oe <= '1';
		end if;
	end if;
end if;
end process;

end Behavioral;