control422.vhd

编码器系统

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    20:09:15 07/14/2007 
-- Design Name: 
-- Module Name:    422control - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity control422 is
port	(	
			clk : in std_logic;
			rst: in std_logic;
			load: in std_logic; 
			data_in : in std_logic_vector(7 downto 0);
			net: out std_logic;
			data_out : out std_logic
		);
end control422;

architecture Behavioral of control422 is

----------------------------------------------------------------------------------------------
-----                                Signal Define                                       -----
----------------------------------------------------------------------------------------------

type state_type is (check_load, q7, q6, q5, q4, q3, q2, q1, q0, end_state);
signal state : state_type;

signal q : std_logic_vector(7 downto 0);
signal counter : integer range 0 to 31;

begin

----------------------------------------------------------------------------------------------
-----                               State Output Logic                                   -----
----------------------------------------------------------------------------------------------
OUTPUT_DECODE : process(clk)
begin
if rising_edge(clk) then

	case (state) is
		
		---------------- Start bit always be zero -----------------
		when check_load =>
			data_out<='0';
			net<='0';
			
			if load='0' then
				q <= data_in;
			else
				q <= "11111111";
			end if;
		
		---------------- Q7 bit transmit -----------------
		when q7 =>
			data_out<=q(7);
			net<='0';
    
		---------------- Q6 bit transmit -----------------
		when q6 =>
			data_out<=q(6);
			net<='0';
			
		---------------- Q5 bit transmit -----------------
		when q5 =>
			data_out<=q(5);
			net<='0';
			
		---------------- Q4 bit transmit -----------------
		when q4 =>
			data_out<=q(4);
			net<='0';
			
		---------------- Q3 bit transmit -----------------
		when q3 =>
			data_out<=q(3);
			net<='0';
			
		---------------- Q2 bit transmit -----------------
		when q2 =>
			data_out<=q(2);
			net<='0';
			
		---------------- Q1 bit transmit -----------------
		when q1 =>
			data_out<=q(1);
			net<='0';
			
		---------------- Q0 bit transmit -----------------
		when q0 =>
			data_out<=q(0);
			net<='0';
			
		---------------- End bit always be one -----------------
		when end_state=>
			data_out<='1';
			net<='1';
			
	end case;
end if;
end process;


----------------------------------------------------------------------------------------------
-----                               State Change Logic                                   -----
----------------------------------------------------------------------------------------------
NEXT_STATE_DECODE : process(clk)
begin
if rising_edge(clk) then
	if rst='1' then
		state <= check_load;
	else

		case (state) is          
                         
			------------- check_load State Change ------------
			when check_load =>
				if counter=24 then
					state <= q7;
				end if;
				
			------------- q7 State Change -------------
			when q7 =>
				if counter=24 then
					state <= q6;
				end if;
             
			------------- q6 State Change -------------
			when q6 =>
				if counter=24 then
					state <= q5;
				end if;

			------------- q5 State Change -------------
			when q5 =>
				if counter=24 then
					state <= q4;
				end if;
				
			------------- q4 State Change -------------
			when q4 =>
				if counter=24 then
					state <= q3;
				end if;
				
			------------- q3 State Change -------------
			when q3 =>
				if counter=24 then
					state <= q2;
				end if;
				
			------------- q2 State Change -------------
			when q2 =>
				if counter=24 then
					state <= q1;
				end if;
				
			------------- q1 State Change -------------
			when q1 =>
				if counter=24 then
					state <= q0;
				end if;
				
			------------- q0 State Change -------------
			when q0 =>
				if counter=24 then
					state <= end_state;
				end if;
				
			------------- end_state State Change -------------
			when end_state =>
				if counter=24 then
					state <= check_load;
				end if;
				
		end case;
	end if;
end if;
end process;

----------------------------------------------------------------------------------------------
-----                       Counter for State Change Logic                               -----
----------------------------------------------------------------------------------------------            

process(clk)
begin
if rising_edge(clk) then
	if counter=24 then
		counter <= 0;
	else
		counter <= counter + 1;
	end if;
end if;
end process;

end Behavioral;