data_src.vhd

编码器系统

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    16:36:00 07/05/2007 
-- Design Name: 
-- Module Name:    data_src - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;

entity data_src is
port	(		
			reset : in std_logic;
			clk : in std_logic;
			vd : out std_logic;
			ccd_clk : out std_logic;
			ccd_data_in : out std_logic_vector(15 downto 0)
		);
end data_src;

architecture Behavioral of data_src is

signal clk_25m : std_logic := '0';
signal ccd_clk_i : std_logic := '0';
signal counter : std_logic_vector(27 downto 0) := (others=>'0');
signal ccd_data_in_tmp : std_logic_vector(15 downto 0) := (others=>'0');

begin

process(clk)
begin
if rising_edge(clk) then
	clk_25m <= not clk_25m;
end if;
end process;

process(clk_25m)
begin
if rising_edge(clk_25m) then
	if reset='1' then
		counter <= (others=>'0');
	elsif counter=x"FFFFFFF" then
		counter <= x"FFFFFFF";
	else
		counter <= counter + 1;
	end if;
end if;
end process;

process(clk_25m)
begin
if rising_edge(clk_25m) then
	if counter<x"0000BB8" then
		vd <= '0';
	else
		vd <= '1';
	end if;
end if;
end process;

process(clk)
begin
if rising_edge(clk) then
	if (counter>x"0000BB8" and counter<x"0A5C949") then
		ccd_clk_i <= clk_25m;
	else
		ccd_clk_i <= '0';
	end if;
end if;
end process;

BUFG_inst : BUFG
port map	(	
				O => ccd_clk,			-- Clock buffer output
				I => ccd_clk_i			-- Clock buffer input
			);

process(clk_25m)
begin
if rising_edge(clk_25m) then
	if (counter>x"0000BB8" and counter<x"0A5C949") then
		ccd_data_in_tmp <= ccd_data_in_tmp + 1;
	else
		ccd_data_in_tmp <= (others=>'0');
	end if;
end if;
end process;

ccd_data_in <= ccd_data_in_tmp;

end Behavioral;