📄 fsm_sdram.vhd
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----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:49:17 07/17/2007
-- Design Name:
-- Module Name: fsm_sdram - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity fsm_sdram is
port (
-- SYSCON signals
sys_clk : in std_logic;
sys_rst : in std_logic;
sys_start : in std_logic;
-- CTRL module data access signals
fifo2sd_full : in std_logic;
fifo2sd_en : out std_logic;
sd2fifo_empty : in std_logic;
sd2fifo_en : out std_logic;
-- SDRAM interface signals
dq_tri_en : out std_logic;
sd_cke : out std_logic;
sd_ck : out std_logic; sd_cs_n : out std_logic; sd_ras_n : out std_logic; sd_cas_n : out std_logic; sd_we_n : out std_logic; sd_dqm : out std_logic_vector(1 downto 0); sd_ba : out std_logic_vector(1 downto 0); sd_a : out std_logic_vector(12 downto 0)
);
end fsm_sdram;
architecture Behavioral of fsm_sdram is
--------------------------------------------------------------------------------------------------- Signal Define ---------------------------------------------------------------------------------------------------
-- State Define
type state_type is ( st_init_1, st_init_2, st_init_3, st_init_4, st_init_5, st_init_6, st_idle_1, st_wr_ref_1, st_wr_ref_2, st_wr_ref_3, st_wr_ref_4, st_wr_1, st_wr_2, st_wr_3, st_wr_4, st_wr_5, st_wr_6, st_idle_2, st_rd_ref_1, st_rd_ref_2, st_rd_ref_3, st_rd_ref_4, st_rd_1, st_rd_2, st_rd_3,
st_rd_4, st_rd_5, st_rd_6, st_idle_1_ref_1, st_idle_1_ref_2, st_idle_2_ref_1, st_idle_2_ref_2 );signal state : state_type;
-- Internal signals
signal init_ref_cnt : std_logic_vector(3 downto 0);
signal ref_cnt : std_logic_vector(7 downto 0);
signal ref_req : std_logic;
signal addr_rd : std_logic_vector(23 downto 0);
signal addr_wr : std_logic_vector(23 downto 0);
signal counter : std_logic_vector(3 downto 0):=(others=>'0');
signal sd_ck_i : std_logic;
begin
--------------------------------------------------------------------------------------------------- State Output Logic ---------------------------------------------------------------------------------------------------
OUTPUT_DECODE: process(sys_clk)
begin
if rising_edge(sys_clk) then
case state is
--------------------------------- SDRAM Init ---------------------------------
when st_init_1 => -- At least 200us delay with nop command when power up
sd_cs_n <= '1';
sd_ras_n <= '1';
sd_cas_n <= '1';
sd_we_n <= '1';
sd_dqm <= "11";
sd_ba <= "00";
sd_a <= (others=>'0');
when st_init_2 => -- Precharge all banks command sd_cs_n <= '0'; sd_ras_n <= '0'; sd_cas_n <= '1'; sd_we_n <= '0'; sd_dqm <= "11"; sd_ba <= "00"; sd_a <= "0010000000000";
when st_init_3 => -- tRP time needed with nop command ( min 20ns ) sd_cs_n <= '1'; sd_ras_n <= '0'; sd_cas_n <= '1'; sd_we_n <= '0'; sd_dqm <= "11"; sd_ba <= "00"; sd_a <= "0010000000000";
when st_init_4 => -- Auto refresh command ( 8 times at least ) sd_cs_n <= '0'; sd_ras_n <= '0'; sd_cas_n <= '0'; sd_we_n <= '1'; sd_dqm <= "11"; sd_ba <= "00"; sd_a <= "0010000000000";
when st_init_5 => -- tRC time needed with nop command ( min 65ns ) sd_cs_n <= '1'; sd_ras_n <= '0'; sd_cas_n <= '0'; sd_we_n <= '1'; sd_dqm <= "11"; sd_ba <= "00"; sd_a <= "0010000000000";
when st_init_6 => -- Mode register set command ( CL=2, BL=1 ) sd_cs_n <= '0'; sd_ras_n <= '0'; sd_cas_n <= '0'; sd_we_n <= '0'; sd_dqm <= "11"; sd_ba <= "00"; sd_a <= "0000000100000";
when st_idle_1 => -- tMRS time needed with nop command ( min 2 clks ) sd_cs_n <= '1'; sd_ras_n <= '1'; sd_cas_n <= '1'; sd_we_n <= '1'; sd_dqm <= "11"; sd_ba <= "00"; sd_a <= (others=>'0');
--------------------------------- SDRAM Write ---------------------------------
when st_wr_ref_1 => -- Auto refresh command sd_cs_n <= '0'; sd_ras_n <= '0'; sd_cas_n <= '0'; sd_we_n <= '1'; sd_dqm <= "11"; sd_ba <= "00"; sd_a <= (others=>'0'); when st_wr_ref_2 => -- tRC time needed with nop command ( min 65ns ) sd_cs_n <= '1'; sd_ras_n <= '0'; sd_cas_n <= '0'; sd_we_n <= '1'; sd_dqm <= "11"; sd_ba <= "00"; sd_a <= (others=>'0'); when st_wr_ref_3 => -- Auto refresh command sd_cs_n <= '0'; sd_ras_n <= '0'; sd_cas_n <= '0'; sd_we_n <= '1'; sd_dqm <= "11"; sd_ba <= "00"; sd_a <= (others=>'0'); when st_wr_ref_4 => -- tRC time needed with nop command ( min 65ns ) sd_cs_n <= '1'; sd_ras_n <= '0'; sd_cas_n <= '0'; sd_we_n <= '1'; sd_dqm <= "11"; sd_ba <= "00"; sd_a <= (others=>'0');
when st_wr_1 => -- Active command sd_cs_n <= '0'; sd_ras_n <= '0'; sd_cas_n <= '1'; sd_we_n <= '1'; sd_dqm <= "11"; sd_ba <= addr_wr(23 downto 22); sd_a <= addr_wr(21 downto 9);
when st_wr_2 => -- tRCD time needed with nop command ( min 20ns ) sd_cs_n <= '1'; sd_ras_n <= '0'; sd_cas_n <= '1'; sd_we_n <= '1'; sd_dqm <= "11"; sd_ba <= addr_wr(23 downto 22); sd_a <= addr_wr(21 downto 9);
when st_wr_3 => -- Write command sd_cs_n <= '0'; sd_ras_n <= '1'; sd_cas_n <= '0'; sd_we_n <= '0'; sd_dqm <= "00"; sd_ba <= addr_wr(23 downto 22); sd_a <= "0000" & addr_wr(8 downto 0);
when st_wr_4 => -- tRDL time needed with nop command ( min 2 clks ) sd_cs_n <= '1'; sd_ras_n <= '1'; sd_cas_n <= '0'; sd_we_n <= '0'; sd_dqm <= "00"; sd_ba <= addr_wr(23 downto 22); sd_a <= "0000" & addr_wr(8 downto 0);
when st_wr_5 => -- Precharge command sd_cs_n <= '0'; sd_ras_n <= '0'; sd_cas_n <= '1'; sd_we_n <= '0'; sd_dqm <= "11"; sd_ba <= addr_wr(23 downto 22); sd_a <= "0010" & addr_wr(8 downto 0);
when st_wr_6 => -- tRP time needed with nop command ( min 20ns ) sd_cs_n <= '1'; sd_ras_n <= '0'; sd_cas_n <= '1'; sd_we_n <= '0'; sd_dqm <= "11"; sd_ba <= addr_wr(23 downto 22); sd_a <= "0010" & addr_wr(8 downto 0);
when st_idle_2 => sd_cs_n <= '1'; sd_ras_n <= '1'; sd_cas_n <= '1'; sd_we_n <= '1'; sd_dqm <= "11"; sd_ba <= "00"; sd_a <= (others=>'0');
--------------------------------- SDRAM Read --------------------------------- when st_rd_ref_1 => -- Auto refresh command sd_cs_n <= '0'; sd_ras_n <= '0'; sd_cas_n <= '0'; sd_we_n <= '1'; sd_dqm <= "11"; sd_ba <= "00"; sd_a <= (others=>'0'); when st_rd_ref_2 => -- tRC time needed with nop command ( min 65ns ) sd_cs_n <= '1'; sd_ras_n <= '0'; sd_cas_n <= '0'; sd_we_n <= '1'; sd_dqm <= "11"; sd_ba <= "00"; sd_a <= (others=>'0'); when st_rd_ref_3 => -- Auto refresh command sd_cs_n <= '0'; sd_ras_n <= '0'; sd_cas_n <= '0'; sd_we_n <= '1'; sd_dqm <= "11"; sd_ba <= "00"; sd_a <= (others=>'0'); when st_rd_ref_4 => -- tRC time needed with nop command ( min 65ns ) sd_cs_n <= '1'; sd_ras_n <= '0'; sd_cas_n <= '0'; sd_we_n <= '1'; sd_dqm <= "11"; sd_ba <= "00"; sd_a <= (others=>'0');
when st_rd_1 => -- Active command sd_cs_n <= '0'; sd_ras_n <= '0'; sd_cas_n <= '1'; sd_we_n <= '1'; sd_dqm <= "11"; sd_ba <= addr_rd(23 downto 22); sd_a <= addr_rd(21 downto 9);
when st_rd_2 => -- tRCD time needed with nop command ( min 20ns ) sd_cs_n <= '1'; sd_ras_n <= '0'; sd_cas_n <= '1'; sd_we_n <= '1'; sd_dqm <= "11"; sd_ba <= addr_rd(23 downto 22); sd_a <= addr_rd(21 downto 9);
when st_rd_3 => -- Read command sd_cs_n <= '0'; sd_ras_n <= '1'; sd_cas_n <= '0'; sd_we_n <= '1'; sd_dqm <= "00"; sd_ba <= addr_rd(23 downto 22); sd_a <= "0000" & addr_rd(8 downto 0);
when st_rd_4 => -- CAS Latency = 2 sd_cs_n <= '1'; sd_ras_n <= '1'; sd_cas_n <= '0'; sd_we_n <= '1'; sd_dqm <= "00"; sd_ba <= addr_rd(23 downto 22); sd_a <= "0000" & addr_rd(8 downto 0);
when st_rd_5 => -- Precharge command sd_cs_n <= '0'; sd_ras_n <= '0'; sd_cas_n <= '1'; sd_we_n <= '0'; sd_dqm <= "11"; sd_ba <= addr_rd(23 downto 22); sd_a <= "0010" & addr_rd(8 downto 0);
when st_rd_6 => -- tRP time needed with nop command ( min 20ns ) sd_cs_n <= '1'; sd_ras_n <= '0'; sd_cas_n <= '1'; sd_we_n <= '0'; sd_dqm <= "11"; sd_ba <= addr_rd(23 downto 22); sd_a <= "0010" & addr_rd(8 downto 0);
---------------------------------- SDRAM Refresh ----------------------------------
when st_idle_1_ref_1 => -- Auto refresh command sd_cs_n <= '0'; sd_ras_n <= '0'; sd_cas_n <= '0'; sd_we_n <= '1'; sd_dqm <= "11"; sd_ba <= "00"; sd_a <= (others=>'0');
when st_idle_1_ref_2 => -- tRC time needed with nop command ( min 65ns ) sd_cs_n <= '1'; sd_ras_n <= '0'; sd_cas_n <= '0'; sd_we_n <= '1'; sd_dqm <= "11"; sd_ba <= "00";⌨️ 快捷键说明
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