transmit_top.vhd

编码器系统

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    15:45:37 12/02/2007 
-- Design Name: 
-- Module Name:    transmit_top - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity transmit_top is
port	(
			clk : in std_logic;
			reset : in std_logic;
			reg : in std_logic_vector(7 downto 0);
			tx : out std_logic
		);
end transmit_top;

architecture Behavioral of transmit_top is

component transmitter is
port	(
			clk : in std_logic;
			reset : in std_logic;
			write : in  std_logic;
			data_in : in std_logic_vector(7 downto 0);
			ready : out std_logic;
			tx : out std_logic
		);
end component;

component transmit_state is
port	(
			clk : in std_logic;
			reset : in std_logic;
			ready : in std_logic;
			reg : in std_logic_vector(7 downto 0);
			write : out std_logic;
			data : out std_logic_vector(7 downto 0)
		);
end component;

signal write : std_logic := '0';
signal ready : std_logic := '0';
signal data : std_logic_vector(7 downto 0) := (others=>'0'); 

begin

inst_transmitter : transmitter
port map	(
				clk => clk,
				reset => reset,
				write => write,
				data_in => data,
				ready => ready,
				tx => tx
			);

inst_transmit_state : transmit_state
port map	(
				clk => clk,
				reset => reset,
				ready => ready,
				reg => reg,
				write => write,
				data => data
			);

end Behavioral;