receiver.vhd

编码器系统

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    20:33:05 12/01/2007 
-- Design Name: 
-- Module Name:    receiver - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity receiver is
port	(
			clk16x : in std_logic;
			reset : in std_logic;
			rx : in std_logic;
			read : out std_logic;
			data_out : out std_logic_vector(7 downto 0)
		);
end receiver;

architecture Behavioral of receiver is

signal counter : std_logic_vector(7 downto 0) := (others=>'0');
signal rsr : std_logic_vector(7 downto 0) := (others=>'0');
signal rx1 : std_logic := '0';
signal hunter : std_logic := '0';

begin

process(clk16x)
begin
if rising_edge(clk16x) then
	if reset='1' then
		counter <= (others=>'0');
	elsif hunter='1' then
		counter <= counter + 1;
	else
		counter <= (others=>'0');
	end if;
end if;
end process;

process(clk16x)
begin
if rising_edge(clk16x) then
	rx1 <= rx;
end if;
end process;

process(clk16x)
begin
if rising_edge(clk16x) then
	if (rx1='1' and rx='0') then						-- Determine the falling edge of the RS data
		hunter <= '1';
	elsif (counter=x"08" and rx='1') then			-- Determine whether the start bit of the RS data 
		hunter <= '0';
	elsif counter=x"98" then
		hunter <= '0';
	end if;
end if;
end process;

process(clk16x)
begin
	if rising_edge(clk16x) then
		if counter=x"18" then
			rsr(7) <= rx;
		elsif counter=x"28" then
			rsr(6) <= rx;
		elsif counter=x"38" then
			rsr(5) <= rx;
		elsif counter=x"48" then
			rsr(4) <= rx;
		elsif counter=x"58" then
			rsr(3) <= rx;
		elsif counter=x"68" then
			rsr(2) <= rx;
		elsif counter=x"78" then
			rsr(1) <= rx;
		elsif counter=x"88" then
			rsr(0) <= rx;
		end if;
	end if;
end process;

process(clk16x)
begin
if rising_edge(clk16x) then
	if (counter=x"98" and rx='1') then				-- Determine whether the stop bit of the RS data
		read <= '1';
	else
		read <= '0';
	end if;
end if;
end process;

process(clk16x)
begin
if rising_edge(clk16x) then
	if (counter=x"98" and rx='1') then
		data_out <= rsr;
	end if;
end if;
end process;

end Behavioral;