ata_ctrl.vhd

编码器系统

begin
if rising_edge(clk) then
	if reset='1' then
		state <= st_init_1;
	else

		case (state) is          
       
--------------------------------
-----  Set ATA Paras     -----
--------------------------------
                         
			------------- st_init_1 State Change ------------
			when st_init_1 =>
				if start_ata='1' then
					state <= st_pmc_1;
				end if;
				
			------------- st_pmc_1 State Change -------------
			when st_pmc_1 =>
				if counter="101" then
					if data_rdy='1' then
						state <= st_pmc_2;
					end if;
				end if;
             
			------------- st_pmc_2 State Change -------------
			when st_pmc_2 =>
				if counter="101" then
					state <= st_pmc_3;
				end if;

			------------- st_pmc_3 State Change -------------
			when st_pmc_3 =>
				if counter="101" then
					state <= st_pmc_4;
				end if;
          
			------------- st_pmc_4 State Change -------------
			when st_pmc_4 =>
				if counter="101" then
					state <= st_pmc_5;
				end if;
             
			------------- st_pmc_5 State Change -------------
			when st_pmc_5 =>
				if counter="101" then
					state <= st_pmc_6;
				end if;
          
			------------- st_pmc_6 State Change -------------
			when st_pmc_6 =>
				if counter="101" then
					state <= st_pmc_7;
				end if;
             
			------------- st_pmc_7 State Change -------------
			when st_pmc_7 =>
				if counter="101" then
					if data_out_pio(6) = '1' then								-- Modified for simulation  (reg(6)= '0')
						state <= st_pmc_8;										-- The Driver is ready to accept command
					end if;
				end if;
          
			------------- st_pmc_8 State Change -------------
			when st_pmc_8 =>
				if counter="101" then
					state <= st_pmc_9;
				end if;
          
			------------- st_pmc_9 State Change -------------
			when st_pmc_9 =>
				if counter_wait="10111" then
                state <= st_we_2;
				end if;

----------------------------
-----  ATA Data Access -----
----------------------------
				
			------------- st_we_1 State Change -------------
			when st_we_1 =>
				if counter="101" then
					if lba_cp(15 downto 0)="1111111111111111" then				-- Write 64K words(128K Byte)
						state <= st_end_1;
					elsif lba_cp(11 downto 0)="111111111111" then				-- Write 4096 words(8K Byte)
						state <= st_we_2;
					end if;
				end if;
             
			------------- st_we_2 State Change -------------
			when st_we_2 =>
				if counter="101" then
					state <= st_we_3;
				end if;
             
			------------- st_we_3 State Change -------------
			when st_we_3 =>
				if counter="101" then
					if (data_out_pio(7)='0' and data_out_pio(3)='1') then			-- The Driver is not busy and have data request
						state <= st_we_1;														-- Modified for simulation  (reg(3)='0')
					end if;
				end if;
       
----------------------------
-----      ATA End      -----
----------------------------
                      
			------------- st_end_1 State Change -------------
			when st_end_1 =>
				if counter="101" then
					state <= st_end_2;
				end if;
             
			------------- st_end_2 State Change -------------
			when st_end_2 =>
				if counter="101" then
					if (data_out_pio(7)='0' and data_out_pio(3)='0') then				-- The Driver is not busy and no data request   
						state <= st_end_3;
					end if;
				end if;
				
			------------- st_end_3 State Change -------------
			when st_end_3 =>
				if counter="101" then
					if lba_cp(23 downto 0)="101001100000000000000000" then 			-- Write 10.375M words2 (actual l028*5356 words) (20.7M Byte)
						state <= st_end_4;
					else
						state <= st_pmc_2;
					end if;
				end if;
				
			------------- st_end_4 State Change -------------
			when st_end_4 =>
				if counter="101" then
					state <= st_pmc_1;
				end if;
          
			------------- Unusual State Change ------------
			when others =>
				state <= st_init_1;
          
		end case;
    
	end if;
end if;
end process;

----------------------------------------------------------------------------------------------
-----                       Counter for State Change Logic                               -----
----------------------------------------------------------------------------------------------            
process(clk)
begin
if rising_edge(clk) then
	if counter="101" then
		counter <= "000";
	else
		counter <= counter + 1;
	end if;
end if;
end process;

process(clk)
begin
if rising_edge(clk) then
	if state=st_pmc_9 then
		counter_wait <= counter_wait + 1;
	else
		counter_wait <= (others=>'0');
	end if;
end if;
end process;

----------------------------------------------------------------------------------------------
-----                             LBA Logic Signals                                      -----
----------------------------------------------------------------------------------------------

process(clk)
begin
if rising_edge(clk) then
	if reset='1' then
		lba_cp <= (others=>'0');
	elsif state=st_we_1 and counter="101" then
		lba_cp <= lba_cp + 1;
	elsif (state=st_end_3 and counter="101" and lba_cp(23 downto 0)="101001100000000000000000") then 			-- Write 10.375M words2 (actual l028*5356 words) (20.7M Byte)
		lba_cp <= (others=>'0');
	end if;
end if;
end process;

process(clk)
begin
if rising_edge(clk) then
	if reset='1' then
		lba <= (others=>'0');
	elsif (dsp_ce0_n='0' and dsp_a=x"04017" and dsp_awe_n='0') then
		lba <= dsp_d_in;
	elsif state=st_end_3 and counter="101" then
		lba <= lba + "100000000";								-- Write 64K words(128K Byte)
	end if;
end if;
end process;

----------------------------------------------------------------------------------------------
-----                          FIFO Interface Signals                                    -----
----------------------------------------------------------------------------------------------

process(clk)
begin
if rising_edge(clk) then
	if counter="001" then
		fifo2ata_clk_i <= '1';
	else
		fifo2ata_clk_i <= '0';
	end if;
end if;
end process;

BUFG_inst : BUFG
port map	(	
				O => fifo2ata_clk,			-- Clock buffer output
				I => fifo2ata_clk_i			-- Clock buffer input
			);
			
process(clk)
begin
if rising_edge(clk) then
	if state=st_we_1 then
		fifo2ata_en <= '1';
	else
		fifo2ata_en <= '0';
	end if;
end if;
end process;

----------------------------------------------------------------------------------------------
-----                 Internal Signal and Static Signal Output Logic                     -----
----------------------------------------------------------------------------------------------

process(clk)
begin
if rising_edge(clk) then
	if reset='1' then
		dd_out_en <= '0';
	elsif we_pio='1' then
		dd_out_en <= '1';
	else
		dd_out_en <= '0';
	end if;
end if;
end process;

process(clk)
begin
if rising_edge(clk) then
	if reset='1' then
		ata_irq <= '1';
	elsif state=st_end_4 then
		ata_irq <= '0';
	else
		ata_irq <= '1';
	end if;
end if;
end process;

dmack_n <= '1';

end Behavioral;