ata_ctrl.vhd

编码器系统

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    15:28:21 07/23/2007 
-- Design Name: 
-- Module Name:    ATA_CTRL - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;

entity ata_ctrl is
port	(	
			-- SYSCON signals
			clk : in std_logic;
			reset : in std_logic;
			start_ata : in std_logic;
			data_rdy : in std_logic;
			ata_irq : out std_logic;
			
			-- DSP signals
			dsp_ce0_n : in std_logic;
			dsp_awe_n : in std_logic;
			dsp_a : in std_logic_vector(21 downto 2);
			dsp_d_in : in std_logic_vector(31 downto 0);
			
			-- CTRL module data access signals
			fifo2ata : in std_logic_vector(15 downto 0);
			fifo2ata_clk : out std_logic;
			fifo2ata_en : out std_logic;
			
			-- ATA interface signals
			dd_out : out std_logic_vector(15 downto 0);
			dd_in : in std_logic_vector(15 downto 0);
			da : out std_logic_vector(2 downto 0);
			cs0_n : out std_logic;
			cs1_n : out std_logic;
			dior_n : out std_logic;
			diow_n : out std_logic;
			dmack_n : out std_logic;
			dd_out_en : out std_logic
		);
end ata_ctrl;

architecture Behavioral of ata_ctrl is
----------------------------------------------------------------------------------------------
-----                            Component Declaration                                   -----
----------------------------------------------------------------------------------------------
component ata_pio_access
port	(	
			clk : in std_logic;
			reset : in std_logic;
			addr : in std_logic_vector(4 downto 0);
			data_out : out std_logic_vector(15 downto 0);
			data_in : in std_logic_vector(15 downto 0);
			we : in std_logic;
			strb : in std_logic;
			dd_out : out std_logic_vector(15 downto 0);
			dd_in : in std_logic_vector(15 downto 0);
			da : out std_logic_vector(2 downto 0);
			cs0_n : out std_logic;
			cs1_n : out std_logic;
			dior_n : out std_logic;
			diow_n : out std_logic
		);
end component;

----------------------------------------------------------------------------------------------
-----                                Signal Define                                       -----
----------------------------------------------------------------------------------------------
-- State Define
type state_type is ( st_init_1, st_pmc_1, st_pmc_2, st_pmc_3, st_pmc_4, st_pmc_5, st_pmc_6, st_pmc_7, st_pmc_8, 
							st_pmc_9, st_we_1, st_we_2, st_we_3, st_end_1, st_end_2, st_end_3, st_end_4 );
signal state : state_type;

-- ATA_PIO_Access component signals
signal strb_pio : std_logic;
signal we_pio : std_logic;
signal addr_pio : std_logic_vector(4 downto 0);
signal data_in_pio : std_logic_vector(15 downto 0);
signal data_out_pio : std_logic_vector(15 downto 0);

-- Internal signals
signal counter : std_logic_vector(2 downto 0);
signal counter_wait : std_logic_vector(4 downto 0);
signal lba : std_logic_vector(31 downto 0);
signal lba_cp : std_logic_vector(23 downto 0);
signal fifo2ata_clk_i : std_logic;

begin

----------------------------------------------------------------------------------------------
-----                            Component Instantiation                                 -----
----------------------------------------------------------------------------------------------
inst_ata_pio_access : ata_pio_access
port map	(	
				clk => clk,
				reset => reset,
				addr => addr_pio,
				data_out => data_out_pio,
				data_in => data_in_pio,
				we => we_pio,
				strb => strb_pio,
				dd_out => dd_out,
				dd_in => dd_in,
				da => da,
				cs0_n => cs0_n,
				cs1_n => cs1_n,
				dior_n => dior_n,
				diow_n => diow_n
			);
 
----------------------------------------------------------------------------------------------
-----                               State Output Logic                                   -----
----------------------------------------------------------------------------------------------
OUTPUT_DECODE : process(clk)
begin
if rising_edge(clk) then

	case (state) is
       
--------------------------------
-----  	Set ATA Paras     -----
--------------------------------
		
		---------------- Wait Start Request -----------------
		when st_init_1 =>
			strb_pio <= '0';
			we_pio <= '0';
		
		---------------- Wait Write Request -----------------
		when st_pmc_1 =>
			strb_pio <= '0';
			we_pio <= '0';
    
		---------------- Write Sector Count Register -----------------
		when st_pmc_2 =>
			strb_pio <= '1';
			addr_pio <= "10010";
			we_pio <= '1';
			data_in_pio <= (others=>'0');
    
		---------------- Write Sector Number Register -----------------
		when st_pmc_3 =>
			strb_pio <= '1';
			addr_pio <= "10011";
			we_pio <= '1';
			data_in_pio(7 downto 0) <= lba(7 downto 0);     
    
		---------------- Write Cylinder Low Register -----------------
		when st_pmc_4 =>
			strb_pio <= '1';
			addr_pio <= "10100";
			we_pio <= '1';
			data_in_pio(7 downto 0) <= lba(15 downto 8); 
    
		---------------- Write Cylinder High Register -----------------
		when st_pmc_5 =>
			strb_pio <= '1';
			addr_pio <= "10101";
			we_pio <= '1';
			data_in_pio(7 downto 0) <= lba(23 downto 16); 
    
		---------------- Write Device/Head Register -----------------
		when st_pmc_6 =>
			strb_pio <= '1';
			addr_pio <= "10110";
			we_pio <= '1';
			data_in_pio(7 downto 0) <= ("1110" & lba(27 downto 24));
    
		---------------- Check the Driver wether be ready to accept command ----------------
		when st_pmc_7 =>
			strb_pio <= '1';
			addr_pio <= "10111";
			we_pio <= '0';
       
		---------------- Write Command ---------------
		when st_pmc_8 =>
			strb_pio <= '1';
			addr_pio <= "10111";
			we_pio <= '1';
			data_in_pio(7 downto 0) <= "11000101";			-- Write Multiple(C5h)
    
		---------------- Wait for driver setup ----------------
		when st_pmc_9 =>
			strb_pio <= '0';
			we_pio <= '0';
    
----------------------------
-----  ATA Data Access -----
----------------------------
    
		---------------- Write to ATA device ----------------
		when st_we_1 =>
			strb_pio <= '1';
			addr_pio <= "10000";
			we_pio <= '1';
			data_in_pio <= fifo2ata;
       
		----------------- Read Alternate Status Register -------------------
		when st_we_2 =>
			strb_pio <= '1';
			addr_pio <= "01110";
			we_pio <= '0';
       
		---------------- Check the driver whether busy or having data request ----------------
		when st_we_3 =>
			strb_pio <= '1';
			addr_pio <= "10111";
			we_pio <= '0';
       
----------------------------
-----      ATA End     -----
----------------------------
    
		----------------- Read Alternate Status Register -------------------
		when st_end_1 =>
			strb_pio <= '1';
			addr_pio <= "01110";
			we_pio <= '0';
    
		---------------- Check the driver whether busy or having data request ----------------
		when st_end_2 =>
			strb_pio <= '1';
			addr_pio <= "10111";
			we_pio <= '0';
			
		---------------- Check over ----------------
		when st_end_3 =>
			strb_pio <= '0';
			we_pio <= '0';
			
		---------------- ATA interrupt generation ----------------
		when st_end_4 =>
			strb_pio <= '0';
			we_pio <= '0';
       
		------------- Unusual State Change ------------
		when others =>
			strb_pio <= '0';
			we_pio <= '0';
       
	end case;

end if;
end process;


----------------------------------------------------------------------------------------------
-----                               State Change Logic                                   -----
----------------------------------------------------------------------------------------------
NEXT_STATE_DECODE : process(clk)