comm_top.vhd

编码器系统

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    15:38:29 12/03/2007 
-- Design Name: 
-- Module Name:    comm_top - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity comm_top is
port	(
			clk : in std_logic;
			reset : in std_logic;
			rx : in std_logic;
			dsp_are_n : in std_logic;
			addr_r : in std_logic_vector(4 downto 0);
			data_out : out std_logic_vector(7 downto 0);
			reg : in std_logic_vector(7 downto 0);          
			tx : out std_logic
		);
end comm_top;

architecture Behavioral of comm_top is

component receive_top
port	(
			clk : in std_logic;
			reset : in std_logic;
			rx : in std_logic;
			dsp_are_n : in std_logic;
			addr_r : in std_logic_vector(4 downto 0);          
			data_out : out std_logic_vector(7 downto 0)
		);
end component;
	
component transmit_top
port	(
			clk : in std_logic;
			reset : in std_logic;
			reg : in std_logic_vector(7 downto 0);          
			tx : out std_logic
		);
end component;

begin

inst_receive_top : receive_top
port map	(
				clk => clk,
				reset => reset,
				rx => rx,
				dsp_are_n => dsp_are_n,
				addr_r => addr_r,
				data_out => data_out
			);

inst_transmit_top : transmit_top
port map	(
				clk => clk,
				reset => reset,
				reg => reg,
				tx => tx
			);

end Behavioral;