dsp_peri.vhd

编码器系统

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    15:59:15 07/19/2007 
-- Design Name: 
-- Module Name:    dsp_peri - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity dsp_peri is
port	(
			fpga_clk_50m : in std_logic;
			reset : in std_logic;
			ata_irq : in std_logic;

			dsp_a : in std_logic_vector(21 downto 6);
			dsp_ce0_n : in std_logic;
			dsp_ce1_n : in std_logic;
			dsp_ce2_n : in std_logic;
			dsp_aoe_n : in std_logic;
			dsp_awe_n : in std_logic;
			dsp_gpio_0 : out std_logic;
			dsp_gpio_1 : out std_logic;
			dsp_gpio_2 : out std_logic;
			dsp_gpio_6 : out std_logic;
			dsp_gpio_7 : out std_logic;
			dsp_int0_n : out std_logic;
			dsp_int1_n : out std_logic;
			dsp_int2_n : out std_logic;
			dsp_int3_n : out std_logic;
			dsp_nmi_n : out std_logic;
			dsp_reset_n : out std_logic;
			dsp_ardy : out std_logic;
			dsp_hcs_n : out std_logic;
			dsp_hold_n : out std_logic;
		
			flash_rst_n : out std_logic;
			flash_ce_n : out std_logic;
			flash_oe_n : out std_logic;
			flash_we_n : out std_logic;
			flash_wp_n : out std_logic;
		
			sram_hce1_n : out std_logic;
			sram_hce2 : out std_logic;
			sram_hoe_n : out std_logic;
			sram_hwe_n : out std_logic;
			sram_hble_n : out std_logic;
			sram_hbhe_n : out std_logic;
		
			sram_lce1_n : out std_logic;
			sram_lce2 : out std_logic;
			sram_loe_n : out std_logic;
			sram_lwe_n : out std_logic;
			sram_lble_n : out std_logic;
			sram_lbhe_n : out std_logic;
		
			adv202_reset_n : out std_logic;
			adv202_cs_n : out std_logic;
			adv202_wr_n : out std_logic;
			adv202_rd_n : out std_logic;
			adv202_dack0_n : out std_logic;
			adv202_dack1_n : out std_logic;
			adv202_irq_n : in std_logic;
			adv202_clk : out std_logic
		);
end dsp_peri;

architecture Behavioral of dsp_peri is

begin

dsp_ardy <= '1';
dsp_hcs_n <= '1';
dsp_hold_n <= '1';
--dsp_reset_n <= not reset;
dsp_reset_n <= '1';				-- DSP Emulation
	
dsp_nmi_n <= '1';
dsp_int0_n <= adv202_irq_n;
dsp_int1_n <= ata_irq;
dsp_int2_n <= '1';
dsp_int3_n <= '1';
	
dsp_gpio_0 <= '1';
dsp_gpio_1 <= '1';
dsp_gpio_2 <= '0';
dsp_gpio_6 <= '1';
dsp_gpio_7 <= '0';

flash_rst_n <= '1';
flash_ce_n <= dsp_ce1_n ;
flash_oe_n <= dsp_aoe_n ;
flash_we_n <= dsp_awe_n;
flash_wp_n <= '1';

sram_hce1_n <= dsp_ce2_n;
sram_hce2 <= not dsp_ce2_n;
sram_hoe_n <= dsp_aoe_n;
sram_hwe_n <= dsp_awe_n;
sram_hble_n <= '0';
sram_hbhe_n <= '0';

sram_lce1_n <= dsp_ce2_n;
sram_lce2 <= not dsp_ce2_n;
sram_loe_n <= dsp_aoe_n;
sram_lwe_n <= dsp_awe_n;
sram_lble_n <= '0';
sram_lbhe_n <= '0';
	
adv202_reset_n <= not reset;
adv202_cs_n <= '0' when (dsp_ce0_n='0' and dsp_a(21 downto 6)=x"0400") else '1';
adv202_wr_n <= '0' when (dsp_ce0_n='0' and dsp_awe_n='0' and dsp_a(21 downto 6)=x"0400") else '1';
adv202_rd_n <= '0' when (dsp_ce0_n='0' and dsp_aoe_n='0' and dsp_a(21 downto 6)=x"0400") else '1';
adv202_dack0_n <= '1';
adv202_dack1_n <= '1';
adv202_clk <= fpga_clk_50m;

end Behavioral;