interface_422.vhd

编码器系统

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    14:31:26 07/31/2007 
-- Design Name: 
-- Module Name:    422interface - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity interface_422 is
port	(
			clk : in std_logic;
			reset: in std_logic;
			data_out : out std_logic;
			dsp_ce0_n : in std_logic;
			dsp_awe_n : in std_logic;
			dsp_aoe_n : in std_logic;
			dsp_a : in std_logic_vector(21 downto 2);
			reg_0 : in std_logic_vector(31 downto 0);
			reg_1 : in std_logic_vector(31 downto 0);
			reg_2 : out std_logic_vector(31 downto 0);
			sram_ce1_n : out std_logic;
			sram_ce2 : out std_logic;
			sram_we_n : out std_logic;
			sram_oe_n : out std_logic;
			sram_addr : out std_logic_vector(19 downto 0);
			sram_addr20 : out std_logic;
			sram_d_in : in std_logic_vector(7 downto 0)
		);
end interface_422;

architecture Behavioral of interface_422 is

component control422 is
port	(	
			clk : in std_logic;
			rst: in std_logic;
			load: in std_logic; 
			data_in : in std_logic_vector(7 downto 0);
			net: out std_logic;
			data_out : out std_logic
		);
end component;

component controlall is
port	(
			clk : in std_logic;
			rst : in std_logic;			
			dsp_ce0_n : in std_logic;
			dsp_awe_n : in std_logic;
			dsp_aoe_n : in std_logic;
			dsp_a : in std_logic_vector(21 downto 2);
			reg_0 : in std_logic_vector(31 downto 0);
			reg_1 : in std_logic_vector(31 downto 0);
			sram_ce1_n : out std_logic;
			sram_ce2 : out std_logic;
			sram_we_n : out std_logic;
			sram_oe_n : out std_logic;
			sram_addr : out std_logic_vector(19 downto 0);
			sram_addr20 : out std_logic;
			sram_d_in : in std_logic_vector(7 downto 0);			
			net : in std_logic;
			load : out std_logic;
			reg_2 : out std_logic_vector(31 downto 0);
			data_422 : out std_logic_vector(7 downto 0)
		);		  
end component;

signal load : std_logic;
signal net : std_logic;
signal data_422 : std_logic_vector(7 downto 0);

begin

inst_control422 : control422
port map	(	
				clk => clk,
				rst => reset,
				load => load,
				data_in => data_422,
				net => net,
				data_out => data_out
			);

inst_controlall : controlall
port map	(
				clk => clk,
				rst => reset,
				dsp_ce0_n => dsp_ce0_n,
				dsp_awe_n => dsp_awe_n,
				dsp_aoe_n => dsp_aoe_n,
				dsp_a => dsp_a,
				reg_0 => reg_0,
				reg_1 => reg_1,
				sram_ce1_n => sram_ce1_n,
				sram_ce2 => sram_ce2,
				sram_we_n => sram_we_n,
				sram_oe_n => sram_oe_n,
				sram_addr => sram_addr,
				sram_addr20 => sram_addr20,
				sram_d_in => sram_d_in,	
				net => net,
				load => load,
				reg_2 => reg_2,
				data_422 => data_422
			);


end Behavioral;