system_tri_io.vhd

编码器系统

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    21:06:36 11/13/2007 
-- Design Name: 
-- Module Name:    system_tri_io - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity system_tri_io is
port	(
			dsp_a : in std_logic_vector(21 downto 2);
			dsp_d : inout std_logic_vector(31 downto 0);
			dsp_d_in : out std_logic_vector(31 downto 0);
			dsp_ce0_n : in std_logic;
			dsp_ce3_n : in std_logic;
			dsp_aoe_n : in std_logic;
						
			sd_dq : inout std_logic_vector(15 downto 0);
			sd_dq_in : out std_logic_vector(15 downto 0);
			sd_dq_out : in std_logic_vector(15 downto 0);
			sd_dq_tri : in std_logic;
			
			dd : inout std_logic_vector(15 downto 0);
			dd_in : out std_logic_vector(15 downto 0);
			fpga_dd_out : in std_logic_vector(15 downto 0);
			reg_3 : in std_logic_vector(31 downto 0);
			dd_tri : in std_logic;
			
			sram_d : inout std_logic_vector(7 downto 0);
			sram_d_in : out std_logic_vector(7 downto 0);
			reg_2 : in std_logic_vector(31 downto 0);
			
			data_out_param : in std_logic_vector(7 downto 0)
		);
			
end system_tri_io;

architecture Behavioral of system_tri_io is

signal dd_in_tmp : std_logic_vector(15 downto 0) := (others=>'0');
signal dsp_d_in_tmp : std_logic_vector(31 downto 0) := (others=>'0');
signal sram_d_in_tmp : std_logic_vector(7 downto 0) := (others=>'0');

begin

dsp_d <= (x"0000" & dd_in_tmp) when (dsp_ce3_n='0' and dsp_aoe_n='0') else
			reg_2 when (dsp_ce0_n='0' and dsp_a=x"04012" and dsp_aoe_n='0') else
			(x"000000" & data_out_param) when (dsp_ce0_n='0' and (dsp_a>x"0401F" and dsp_a<x"04040") and dsp_aoe_n='0') else
			(x"000000" & sram_d_in_tmp) when (dsp_ce0_n='0' and dsp_a>x"04fff" and dsp_aoe_n='0') else (others=>'Z');
dsp_d_in_tmp <= dsp_d;

sd_dq <= sd_dq_out when sd_dq_tri='1' else (others=>'Z');
sd_dq_in <= sd_dq;

dd <= dsp_d_in_tmp(15 downto 0) when (reg_3=x"00000000" and dsp_ce3_n='0' and dsp_aoe_n='1') else
		fpga_dd_out when (reg_3=x"00000055" and dd_tri='1') else (others=>'Z');
dd_in_tmp <= dd;

sram_d <= dsp_d_in_tmp(7 downto 0) when (dsp_ce0_n='0' and dsp_a > x"04fff" and dsp_aoe_n='1') else (others=>'Z');
sram_d_in_tmp <= sram_d;

dd_in <= dd_in_tmp;
dsp_d_in <= dsp_d_in_tmp;
sram_d_in <= sram_d_in_tmp;

end Behavioral;