controlall.vhd

编码器系统

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    21:06:45 07/15/2007 
-- Design Name: 
-- Module Name:    controlall - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity controlall is
port	(
			-- SYSCON signals
			clk : in std_logic;
			rst : in std_logic;
			
			dsp_ce0_n : in std_logic;
			dsp_awe_n : in std_logic;
			dsp_aoe_n : in std_logic;
			dsp_a : in std_logic_vector(21 downto 2);
			reg_0 : in std_logic_vector(31 downto 0);
			reg_1 : in std_logic_vector(31 downto 0);
		
			-- SRAM signals
			sram_ce1_n : out std_logic;
			sram_ce2 : out std_logic;
			sram_we_n : out std_logic;
			sram_oe_n : out std_logic;
			sram_addr : out std_logic_vector(19 downto 0);
			sram_addr20 : out std_logic;
			sram_d_in : in std_logic_vector(7 downto 0);
			
			-- Handshaking signals
			net : in std_logic;
			load : out std_logic;
			reg_2 : out std_logic_vector(31 downto 0);
			
			-- Parallel output data
			data_422 : out std_logic_vector(7 downto 0)
		);		  
end controlall;

architecture Behavioral of controlall is

----------------------------------------------------------------------------------------------
-----                                Signal Define                                       -----
----------------------------------------------------------------------------------------------
-- State Define
type state_type is (	idle, dsp_writeto_sram, read_sram_ready, read_sram_idle, sram_r_c0, sram_r_c1, sram_r_c2,
							sram_r_c3 );
signal state: state_type;

-- Internal signals
signal address : std_logic_vector(19 downto 0);
signal counter : std_logic_vector(31 downto 0);
signal counter1 : integer range 0 to 31;

begin

----------------------------------------------------------------------------------------------
-----                               State Output Logic                                   -----
----------------------------------------------------------------------------------------------
OUTPUT_DECODE : process(clk)
begin
if rising_edge(clk) then

	case (state) is
		
		---------------- Idle State -----------------
		when idle =>
			reg_2(7 downto 0) <= x"55";
			load <= '1';
			data_422 <= (others=>'0');
		
		---------------- DSP write to SRAM -----------------
		when dsp_writeto_sram =>
			reg_2(7 downto 0) <= x"aa";
			load <= '1';
    
		---------------- Ready to read SRAM : intend to clear counter -----------------
		when read_sram_ready =>
			reg_2(7 downto 0) <= x"aa";
			load <= '1';

		---------------- Idle to read SRAM -----------------
		when read_sram_idle =>
			reg_2(7 downto 0) <= x"aa";	
			load <= '1';

		---------------- Read SRAM Stage 0 -----------------
		when sram_r_c0 =>
			reg_2(7 downto 0) <= x"aa";
			load <= '1';

		---------------- Read SRAM Stage 1 -----------------
		when sram_r_c1 =>
			reg_2(7 downto 0) <= x"aa";
			load <= '0';
			data_422 <= sram_d_in;
			
		---------------- Read SRAM Stage 2 -----------------
		when sram_r_c2 =>
			reg_2(7 downto 0) <= x"aa";
			load <= '0';
			
		---------------- Read SRAM Stage 3 -----------------
		when sram_r_c3 =>
			reg_2(7 downto 0) <= x"aa";
			load <= '0';
			
	end case;
end if;
end process;


----------------------------------------------------------------------------------------------
-----                               State Change Logic                                   -----
----------------------------------------------------------------------------------------------
NEXT_STATE_DECODE : process(clk)
begin
if rising_edge(clk) then
	if rst='1' then
		state <= idle;
	else

		case (state) is          
                         
			------------- idle State Change ------------
			when idle =>
				if reg_0=x"00000055" then
					state <= dsp_writeto_sram;
				end if;
				
			---------------- dsp_writeto_sram -----------------
			when dsp_writeto_sram =>
				if  reg_0=x"000000AA"  then
					state <= read_sram_ready;
				end if;
		 
			---------------- read_sram_ready -----------------
			when read_sram_ready =>
				state <= read_sram_idle;
	
			---------------- read_sram_idle -----------------
			when read_sram_idle =>
				if net='1' then
					state <= sram_r_c0;
				end if;
	
			---------------- sram_r_c0 -----------------
			when sram_r_c0 =>
				if counter1=15 then
					state <= sram_r_c1;
				end if;
	
			---------------- sram_r_c1 -----------------
			when sram_r_c1 =>
				if counter1=15 then
					state <= sram_r_c2;
				end if;
				
			---------------- sram_r_c2 -----------------
			when sram_r_c2 =>
				if counter1=15 then
					state <= sram_r_c3;
				end if;
				
			---------------- sram_r_c3 -----------------
			when sram_r_c3 =>
				if counter1=15 and counter=reg_1 then						-- reg_1 must be the number-1
					state <= idle;
				elsif counter1=15 then
					state <= read_sram_idle;
				end if;
				
		end case;
	end if;
end if;
end process;


----------------------------------------------------------------------------------------------
-----                       Counter for State Change Logic                               -----
----------------------------------------------------------------------------------------------            

process(clk)
begin
if rising_edge(clk) then
	if (counter1=15 or state=read_sram_idle) then
		counter1 <= 0;
	else
		counter1 <= counter1 + 1;
	end if;
end if;
end process;


----------------------------------------------------------------------------------------------
-----                       	Counter for Data Count Logic                               -----
----------------------------------------------------------------------------------------------            

process(clk)
begin
if rising_edge(clk) then
	if state=read_sram_ready then
		counter <= (others=>'0');
	elsif (state=sram_r_c3 and counter1=15) then
		counter <= counter + 1;
	end if;
end if;
end process;

----------------------------------------------------------------------------------------------
-----                       			SRAM Address Logic     		                          -----
---------------------------------------------------------------------------------------------- 

process(clk)
begin
if rising_edge(clk) then
	if state=read_sram_ready then
		address <= x"08000";
	elsif (state=sram_r_c3 and counter1=15) then
		address <= address + 1;
	end if;
end if;
end process;


----------------------------------------------------------------------------------------------
-----                       			SRAM Control Logic     		                          -----
----------------------------------------------------------------------------------------------
				
sram_ce1_n <= '0' when ((state=dsp_writeto_sram and dsp_ce0_n='0' and dsp_a > x"04fff") or state=sram_r_c0 or state=sram_r_c1) else '1';
sram_ce2 <= '1' when ((state=dsp_writeto_sram and dsp_ce0_n='0' and dsp_a > x"04fff") or state=sram_r_c0 or state=sram_r_c1) else '0';
sram_we_n <= '0' when (state=dsp_writeto_sram and dsp_awe_n='0') else '1';
sram_oe_n <= '0' when ((state=dsp_writeto_sram and dsp_aoe_n='0') or state=sram_r_c0 or state=sram_r_c1) else '1';
sram_addr <= dsp_a when state=dsp_writeto_sram else address;
					

----------------------------------------------------------------------------------------------
-----                       			State Control Regs     		                          -----
----------------------------------------------------------------------------------------------

-- reg_0=x"00000055" means idel state to dspwritetosram state
-- reg_0=x"000000AA" means dspwritetosram state to readsramready state
-- reg_1 record the data number to be transfered

sram_addr20 <= '0';
reg_2(31 downto 8) <= (others=>'0');

-- reg_2=x"00000055" means 422 idle
-- reg_2=x"000000aa" means 422 busy

end Behavioral;