📄 mcf5206.h
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/*
* File: src/include/cpu/coldfire/mcf5206.h
* Purpose: MCF5206 definitions
*
* Notes: This file automatically included.
*
*
* Modifications:
*
*/
#ifndef _CPU_MCF5206_H
#define _CPU_MCF5206_H
/***********************************************************************/
/*
* Cache and Access Control Register routines and defintions
*/
#define MCF5206_CACR_CENB (0x80000000)
#define MCF5206_CACR_CFRZ (0x08000000)
#define MCF5206_CACR_CINV (0x01000000)
#define MCF5206_CACR_CMOD (0x00000200)
#define MCF5206_CACR_CWRP (0x00000020)
#define MCF5206_CACR_CLNF_00 (0x00000000)
#define MCF5206_CACR_CLNF_01 (0x00000001)
#define MCF5206_CACR_CLNF_10 (0x00000002)
#define MCF5206_ACR_BASE(a) ((a)&0xFF000000)
#define MCF5206_ACR_MASK(a) (((a)&0xFF000000) >> 8)
#define MCF5206_ACR_EN (0x00008000)
#define MCF5206_ACR_S_USER (0x00000000)
#define MCF5206_ACR_S_SUPER (0x00002000)
#define MCF5206_ACR_S_IGNORE (0x00006000)
#define MCF5206_ACR_ENIB (0x00000080)
#define MCF5206_ACR_CM (0x00000040)
#define MCF5206_ACR_WP (0x00000004)
#define MCF5206_SRAMBAR_BASE(a) ((a)&0xFFFFFE00)
#define MCF5206_SRAMBAR_WP (0x00000100)
#define MCF5206_SRAMBAR_AS_CI (0x00000080)
#define MCF5206_SRAMBAR_AS_SC (0x00000040)
#define MCF5206_SRAMBAR_AS_SD (0x00000020)
#define MCF5206_SRAMBAR_AS_UC (0x00000004)
#define MCF5206_SRAMBAR_AS_UD (0x00000002)
#define MCF5206_SRAMBAR_V (0x00000001)
#define MCF5206_MBAR_BASE(a) ((a)&0xFFFFFC00)
#define MCF5206_MBAR_SC (0x00000010)
#define MCF5206_MBAR_SD (0x00000008)
#define MCF5206_MBAR_UC (0x00000004)
#define MCF5206_MBAR_UD (0x00000002)
#define MCF5206_MBAR_V (0x00000001)
/***********************************************************************/
/*
* Macro for computing address of on-chip peripheral registers
*/
#define Mcf5206_addr(IMMP,OFFSET) ((void *)&((uint8 *)IMMP)[OFFSET])
/*
* Macros for accessing the on-chip I/O resources
*/
#define Mcf5206_iord(IMMP,OFFSET,SIZE) \
*(volatile uint ## SIZE *)(Mcf5206_addr(IMMP,OFFSET))
#define Mcf5206_iowr(IMMP,OFFSET,SIZE,DATA) \
*(volatile uint ## SIZE *)(Mcf5206_addr(IMMP,OFFSET)) = (DATA)
/***********************************************************************/
/*
* System Integration Modules, SIM
*/
/* Offsets of the registers from the MBAR */
#define MCF5206_SIM_SIMR (0x0003)
#define MCF5206_SIM_ICR1 (0x0014)
#define MCF5206_SIM_ICR2 (0x0015)
#define MCF5206_SIM_ICR3 (0x0016)
#define MCF5206_SIM_ICR4 (0x0017)
#define MCF5206_SIM_ICR5 (0x0018)
#define MCF5206_SIM_ICR6 (0x0019)
#define MCF5206_SIM_ICR7 (0x001A)
#define MCF5206_SIM_ICR8 (0x001B)
#define MCF5206_SIM_ICR9 (0x001C)
#define MCF5206_SIM_ICR10 (0x001D)
#define MCF5206_SIM_ICR11 (0x001E)
#define MCF5206_SIM_ICR12 (0x001F)
#define MCF5206_SIM_ICR13 (0x0020)
#if (defined (CPU_MCF5206e))
#define MCF5206_SIM_ICR14 (0x0021)
#define MCF5206_SIM_ICR15 (0x0022)
#endif
#define MCF5206_SIM_IMR (0x0036)
#define MCF5206_SIM_IPR (0x003A)
#define MCF5206_SIM_RSR (0x0040)
#define MCF5206_SIM_SYPCR (0x0041)
#define MCF5206_SIM_SWIVR (0x0042)
#define MCF5206_SIM_SWSR (0x0043)
#if (defined (CPU_MCF5206e))
#define MCF5206_SIM_PAR (0x00CA)
#else
#define MCF5206_SIM_PAR (0x00CB)
#endif
/* Read access macros for general use */
#define MCF5206_RD_SIM_SIMR(IMMP) Mcf5206_iord(IMMP,MCF5206_SIM_SIMR,8)
#define MCF5206_RD_SIM_ICR1(IMMP) Mcf5206_iord(IMMP,MCF5206_SIM_ICR1,8)
#define MCF5206_RD_SIM_ICR2(IMMP) Mcf5206_iord(IMMP,MCF5206_SIM_ICR2,8)
#define MCF5206_RD_SIM_ICR3(IMMP) Mcf5206_iord(IMMP,MCF5206_SIM_ICR3,8)
#define MCF5206_RD_SIM_ICR4(IMMP) Mcf5206_iord(IMMP,MCF5206_SIM_ICR4,8)
#define MCF5206_RD_SIM_ICR5(IMMP) Mcf5206_iord(IMMP,MCF5206_SIM_ICR5,8)
#define MCF5206_RD_SIM_ICR6(IMMP) Mcf5206_iord(IMMP,MCF5206_SIM_ICR6,8)
#define MCF5206_RD_SIM_ICR7(IMMP) Mcf5206_iord(IMMP,MCF5206_SIM_ICR7,8)
#define MCF5206_RD_SIM_ICR8(IMMP) Mcf5206_iord(IMMP,MCF5206_SIM_ICR8,8)
#define MCF5206_RD_SIM_ICR9(IMMP) Mcf5206_iord(IMMP,MCF5206_SIM_ICR9,8)
#define MCF5206_RD_SIM_ICR10(IMMP) Mcf5206_iord(IMMP,MCF5206_SIM_ICR10,8)
#define MCF5206_RD_SIM_ICR11(IMMP) Mcf5206_iord(IMMP,MCF5206_SIM_ICR11,8)
#define MCF5206_RD_SIM_ICR12(IMMP) Mcf5206_iord(IMMP,MCF5206_SIM_ICR12,8)
#define MCF5206_RD_SIM_ICR13(IMMP) Mcf5206_iord(IMMP,MCF5206_SIM_ICR13,8)
#if (defined (CPU_MCF5206e))
#define MCF5206_RD_SIM_ICR14(IMMP) Mcf5206_iord(IMMP,MCF5206_SIM_ICR14,8)
#define MCF5206_RD_SIM_ICR15(IMMP) Mcf5206_iord(IMMP,MCF5206_SIM_ICR15,8)
#endif
#define MCF5206_RD_SIM_IMR(IMMP) Mcf5206_iord(IMMP,MCF5206_SIM_IMR,16)
#define MCF5206_RD_SIM_IPR(IMMP) Mcf5206_iord(IMMP,MCF5206_SIM_IPR,16)
#define MCF5206_RD_SIM_RSR(IMMP) Mcf5206_iord(IMMP,MCF5206_SIM_RSR,8)
#define MCF5206_RD_SIM_SYPCR(IMMP) Mcf5206_iord(IMMP,MCF5206_SIM_SYPCR,8)
#define MCF5206_RD_SIM_SWIVR(IMMP) Mcf5206_iord(IMMP,MCF5206_SIM_SWIVR,8)
#if (defined (CPU_MCF5206e))
#define MCF5206_RD_SIM_PAR(IMMP) Mcf5206_iord(IMMP,MCF5206_SIM_PAR,16)
#else
#define MCF5206_RD_SIM_PAR(IMMP) Mcf5206_iord(IMMP,MCF5206_SIM_PAR,8)
#endif
/* Write access macros for general use */
#define MCF5206_WR_SIM_SIMR(IMMP,DATA) \
Mcf5206_iowr(IMMP,MCF5206_SIM_SIMR,8,DATA)
#define MCF5206_WR_SIM_ICR1(IMMP,DATA) \
Mcf5206_iowr(IMMP,MCF5206_SIM_ICR1,8,DATA)
#define MCF5206_WR_SIM_ICR2(IMMP,DATA) \
Mcf5206_iowr(IMMP,MCF5206_SIM_ICR2,8,DATA)
#define MCF5206_WR_SIM_ICR3(IMMP,DATA) \
Mcf5206_iowr(IMMP,MCF5206_SIM_ICR3,8,DATA)
#define MCF5206_WR_SIM_ICR4(IMMP,DATA) \
Mcf5206_iowr(IMMP,MCF5206_SIM_ICR4,8,DATA)
#define MCF5206_WR_SIM_ICR5(IMMP,DATA) \
Mcf5206_iowr(IMMP,MCF5206_SIM_ICR5,8,DATA)
#define MCF5206_WR_SIM_ICR6(IMMP,DATA) \
Mcf5206_iowr(IMMP,MCF5206_SIM_ICR6,8,DATA)
#define MCF5206_WR_SIM_ICR7(IMMP,DATA) \
Mcf5206_iowr(IMMP,MCF5206_SIM_ICR7,8,DATA)
#define MCF5206_WR_SIM_ICR8(IMMP,DATA) \
Mcf5206_iowr(IMMP,MCF5206_SIM_ICR8,8,DATA)
#define MCF5206_WR_SIM_ICR9(IMMP,DATA) \
Mcf5206_iowr(IMMP,MCF5206_SIM_ICR9,8,DATA)
#define MCF5206_WR_SIM_ICR10(IMMP,DATA) \
Mcf5206_iowr(IMMP,MCF5206_SIM_ICR10,8,DATA)
#define MCF5206_WR_SIM_ICR11(IMMP,DATA) \
Mcf5206_iowr(IMMP,MCF5206_SIM_ICR11,8,DATA)
#define MCF5206_WR_SIM_ICR12(IMMP,DATA) \
Mcf5206_iowr(IMMP,MCF5206_SIM_ICR12,8,DATA)
#define MCF5206_WR_SIM_ICR13(IMMP,DATA) \
Mcf5206_iowr(IMMP,MCF5206_SIM_ICR13,8,DATA)
#if (defined(CPU_MCF5206e))
#define MCF5206_WR_SIM_ICR14(IMMP,DATA) \
Mcf5206_iowr(IMMP,MCF5206_SIM_ICR14,8,DATA)
#define MCF5206_WR_SIM_ICR15(IMMP,DATA) \
Mcf5206_iowr(IMMP,MCF5206_SIM_ICR15,8,DATA)
#endif
#define MCF5206_WR_SIM_IMR(IMMP,DATA) \
Mcf5206_iowr(IMMP,MCF5206_SIM_IMR,16,DATA)
#define MCF5206_WR_SIM_RSR(IMMP,DATA) \
Mcf5206_iowr(IMMP,MCF5206_SIM_RSR,8,DATA)
#define MCF5206_WR_SIM_SYPCR(IMMP,DATA) \
Mcf5206_iowr(IMMP,MCF5206_SIM_SYPCR,8,DATA)
#define MCF5206_WR_SIM_SWIVR(IMMP,DATA) \
Mcf5206_iowr(IMMP,MCF5206_SIM_SWIVR,8,DATA)
#define MCF5206_WR_SIM_SWSR(IMMP,DATA) \
Mcf5206_iowr(IMMP,MCF5206_SIM_SWSR,8,DATA)
#if (defined (CPU_MCF5206e))
#define MCF5206_WR_SIM_PAR(IMMP,DATA) \
Mcf5206_iowr(IMMP,MCF5206_SIM_PAR,16,DATA)
#else
#define MCF5206_WR_SIM_PAR(IMMP,DATA) \
Mcf5206_iowr(IMMP,MCF5206_SIM_PAR,8,DATA)
#endif
#if 1
typedef volatile struct
{
uint8 reserved0;
uint8 reserved1;
uint8 reserved2;
uint8 SIMR;
uint32 reserved3;
uint32 reserved4;
uint32 reserved5;
uint32 reserved6;
uint8 ICR1;
uint8 ICR2;
uint8 ICR3;
uint8 ICR4;
uint8 ICR5;
uint8 ICR6;
uint8 ICR7;
uint8 ICR8;
uint8 ICR9;
uint8 ICR10;
uint8 ICR11;
uint8 ICR12;
uint8 ICR13;
#if (defined (CPU_MCF5206e))
uint8 ICR14;
uint8 ICR15;
#else
uint8 reserved7;
uint8 reserved8;
#endif
uint8 reserved9;
uint32 reserved10[4];
uint8 reserved11;
uint8 reserved12;
uint16 IMR;
uint16 reserved13;
uint16 IPR;
uint32 reserved14;
uint8 RSR;
uint8 SYPCR;
uint8 SWIVR;
uint8 SWSR;
uint8 reserved31[135];
#if (defined (CPU_MCF5206e))
uint16 PAR;
#else
uint8 PAR;
#endif
} MCF5206_SIM;
#endif
#define MCF5206_SIM_SIMR_FRZ1 (0x80)
#define MCF5206_SIM_SIMR_FRZ0 (0x40)
#define MCF5206_SIM_SIMR_BL (0x01)
#define MCF5206_SIM_ICR_AVEC (0x80)
#define MCF5206_SIM_ICR_IL(a) (((a)&0x07)<<2)
#define MCF5206_SIM_ICR_IP(a) (((a)&0x03))
#define MCF5206_SIM_IMR_UART1 (0x2000)
#define MCF5206_SIM_IMR_UART0 (0x1000)
#define MCF5206_SIM_IMR_I2C (0x0800)
#define MCF5206_SIM_IMR_TIMER1 (0x0400)
#define MCF5206_SIM_IMR_TIMER0 (0x0200)
#define MCF5206_SIM_IMR_SWT (0x0100)
#define MCF5206_SIM_IMR_EINT7 (0x0080)
#define MCF5206_SIM_IMR_EINT6 (0x0040)
#define MCF5206_SIM_IMR_EINT5 (0x0020)
#define MCF5206_SIM_IMR_EINT4 (0x0010)
#define MCF5206_SIM_IMR_EINT3 (0x0008)
#define MCF5206_SIM_IMR_EINT2 (0x0004)
#define MCF5206_SIM_IMR_EINT1 (0x0002)
#define MCF5206_SIM_IPR_UART1 (0x2000)
#define MCF5206_SIM_IPR_UART0 (0x1000)
#define MCF5206_SIM_IPR_I2C (0x0800)
#define MCF5206_SIM_IPR_T2 (0x0400)
#define MCF5206_SIM_IPR_T1 (0x0200)
#define MCF5206_SIM_IPR_SWT (0x0100)
#define MCF5206_SIM_IPR_EINT7 (0x0080)
#define MCF5206_SIM_IPR_EINT6 (0x0040)
#define MCF5206_SIM_IPR_EINT5 (0x0020)
#define MCF5206_SIM_IPR_EINT4 (0x0010)
#define MCF5206_SIM_IPR_EINT3 (0x0008)
#define MCF5206_SIM_IPR_EINT2 (0x0004)
#define MCF5206_SIM_IPR_EINT1 (0x0002)
#define MCF5206_SIM_RSR_HRST (0x80)
#define MCF5206_SIM_RSR_SWTR (0x20)
#define MCF5206_SIM_SYPCR_SWE (0x80)
#define MCF5206_SIM_SYPCR_SWRI (0x40)
#define MCF5206_SIM_SYPCR_SWT_2_9 (0x00)
#define MCF5206_SIM_SYPCR_SWT_2_11 (0x08)
#define MCF5206_SIM_SYPCR_SWT_2_13 (0x10)
#define MCF5206_SIM_SYPCR_SWT_2_15 (0x18)
#define MCF5206_SIM_SYPCR_SWT_2_18 (0x20)
#define MCF5206_SIM_SYPCR_SWT_2_20 (0x28)
#define MCF5206_SIM_SYPCR_SWT_2_22 (0x30)
#define MCF5206_SIM_SYPCR_SWT_2_24 (0x38)
#define MCF5206_SIM_SYPCR_BME (0x04)
#define MCF5206_SIM_SYPCR_BM_1024 (0x00)
#define MCF5206_SIM_SYPCR_BM_512 (0x01)
#define MCF5206_SIM_SYPCR_BM_256 (0x02)
#define MCF5206_SIM_SYPCR_BM_128 (0x03)
#define MCF5206_SIM_SWIVR_SWIV(a) ((a)&0x00FF)
#define MCF5206_SIM_PAR_PAR7 (0x80)
#define MCF5206_SIM_PAR_PAR7_RSTO (0x00)
#define MCF5206_SIM_PAR_PAR7_RTS2 (0x80)
#define MCF5206_SIM_PAR_PAR6 (0x40)
#define MCF5206_SIM_PAR_PAR6_IRQ (0x00)
#define MCF5206_SIM_PAR_PAR6_IPL (0x40)
#define MCF5206_SIM_PAR_PAR5 (0x20)
#define MCF5206_SIM_PAR_PAR5_PP74 (0x00)
#define MCF5206_SIM_PAR_PAR5_PST (0x20)
#define MCF5206_SIM_PAR_PAR4 (0x10)
#define MCF5206_SIM_PAR_PAR4_PP30 (0x00)
#define MCF5206_SIM_PAR_PAR4_DDATA (0x10)
#define MCF5206_SIM_PAR_PAR3 (0x08)
#define MCF5206_SIM_PAR_PAR2 (0x04)
#define MCF5206_SIM_PAR_PAR1 (0x02)
#define MCF5206_SIM_PAR_PAR0 (0x01)
/***********************************************************************/
/*
* Chip-Select Module, CS
*/
/* Offsets of the registers from the MBAR */
#define MCF5206_CS_CSAR0 (0x0064)
#define MCF5206_CS_CSMR0 (0x0068)
#define MCF5206_CS_CSCR0 (0x006E)
#define MCF5206_CS_CSAR1 (0x0070)
#define MCF5206_CS_CSMR1 (0x0074)
#define MCF5206_CS_CSCR1 (0x007A)
#define MCF5206_CS_CSAR2 (0x007C)
#define MCF5206_CS_CSMR2 (0x0080)
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