mcf5206.h
来自「motorola 针对coldfire 5275 评估板的Dbug bootlo」· C头文件 代码 · 共 1,360 行 · 第 1/4 页
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#define MCF5206_CS_CSCR2 (0x0086)
#define MCF5206_CS_CSAR3 (0x0088)
#define MCF5206_CS_CSMR3 (0x008C)
#define MCF5206_CS_CSCR3 (0x0092)
#define MCF5206_CS_CSAR4 (0x0094)
#define MCF5206_CS_CSMR4 (0x0098)
#define MCF5206_CS_CSCR4 (0x009E)
#define MCF5206_CS_CSAR5 (0x00A0)
#define MCF5206_CS_CSMR5 (0x00A4)
#define MCF5206_CS_CSCR5 (0x00AA)
#define MCF5206_CS_CSAR6 (0x00AC)
#define MCF5206_CS_CSMR6 (0x00B0)
#define MCF5206_CS_CSCR6 (0x00B6)
#define MCF5206_CS_CSAR7 (0x00B8)
#define MCF5206_CS_CSMR7 (0x00BC)
#define MCF5206_CS_CSCR7 (0x00C2)
#define MCF5206_CS_DMCR (0x00C6)
/* Read access macros for general use */
#define MCF5206_RD_CS_CSAR0(IMMP) Mcf5206_iord(IMMP,MCF5206_CS_CSAR0,16)
#define MCF5206_RD_CS_CSMR0(IMMP) Mcf5206_iord(IMMP,MCF5206_CS_CSMR0,32)
#define MCF5206_RD_CS_CSCR0(IMMP) Mcf5206_iord(IMMP,MCF5206_CS_CSCR0,16)
#define MCF5206_RD_CS_CSAR1(IMMP) Mcf5206_iord(IMMP,MCF5206_CS_CSAR1,16)
#define MCF5206_RD_CS_CSMR1(IMMP) Mcf5206_iord(IMMP,MCF5206_CS_CSMR1,32)
#define MCF5206_RD_CS_CSCR1(IMMP) Mcf5206_iord(IMMP,MCF5206_CS_CSCR1,16)
#define MCF5206_RD_CS_CSAR2(IMMP) Mcf5206_iord(IMMP,MCF5206_CS_CSAR2,16)
#define MCF5206_RD_CS_CSMR2(IMMP) Mcf5206_iord(IMMP,MCF5206_CS_CSMR2,32)
#define MCF5206_RD_CS_CSCR2(IMMP) Mcf5206_iord(IMMP,MCF5206_CS_CSCR2,16)
#define MCF5206_RD_CS_CSAR3(IMMP) Mcf5206_iord(IMMP,MCF5206_CS_CSAR3,16)
#define MCF5206_RD_CS_CSMR3(IMMP) Mcf5206_iord(IMMP,MCF5206_CS_CSMR3,32)
#define MCF5206_RD_CS_CSCR3(IMMP) Mcf5206_iord(IMMP,MCF5206_CS_CSCR3,16)
#define MCF5206_RD_CS_CSAR4(IMMP) Mcf5206_iord(IMMP,MCF5206_CS_CSAR4,16)
#define MCF5206_RD_CS_CSMR4(IMMP) Mcf5206_iord(IMMP,MCF5206_CS_CSMR4,32)
#define MCF5206_RD_CS_CSCR4(IMMP) Mcf5206_iord(IMMP,MCF5206_CS_CSCR4,16)
#define MCF5206_RD_CS_CSAR5(IMMP) Mcf5206_iord(IMMP,MCF5206_CS_CSAR5,16)
#define MCF5206_RD_CS_CSMR5(IMMP) Mcf5206_iord(IMMP,MCF5206_CS_CSMR5,32)
#define MCF5206_RD_CS_CSCR5(IMMP) Mcf5206_iord(IMMP,MCF5206_CS_CSCR5,16)
#define MCF5206_RD_CS_CSAR6(IMMP) Mcf5206_iord(IMMP,MCF5206_CS_CSAR6,16)
#define MCF5206_RD_CS_CSMR6(IMMP) Mcf5206_iord(IMMP,MCF5206_CS_CSMR6,32)
#define MCF5206_RD_CS_CSCR6(IMMP) Mcf5206_iord(IMMP,MCF5206_CS_CSCR6,16)
#define MCF5206_RD_CS_CSAR7(IMMP) Mcf5206_iord(IMMP,MCF5206_CS_CSAR7,16)
#define MCF5206_RD_CS_CSMR7(IMMP) Mcf5206_iord(IMMP,MCF5206_CS_CSMR7,32)
#define MCF5206_RD_CS_CSCR7(IMMP) Mcf5206_iord(IMMP,MCF5206_CS_CSCR7,16)
#define MCF5206_RD_CS_DMCR(IMMP) Mcf5206_iord(IMMP,MCF5206_CS_DMCR,16)
/* Write access macros for general use */
#define MCF5206_WR_CS_CSAR0(IMMP,DATA) \
Mcf5206_iowr(IMMP,MCF5206_CS_CSAR0,16,DATA)
#define MCF5206_WR_CS_CSMR0(IMMP,DATA) \
Mcf5206_iowr(IMMP,MCF5206_CS_CSMR0,32,DATA)
#define MCF5206_WR_CS_CSCR0(IMMP,DATA) \
Mcf5206_iowr(IMMP,MCF5206_CS_CSCR0,16,DATA)
#define MCF5206_WR_CS_CSAR1(IMMP,DATA) \
Mcf5206_iowr(IMMP,MCF5206_CS_CSAR1,16,DATA)
#define MCF5206_WR_CS_CSMR1(IMMP,DATA) \
Mcf5206_iowr(IMMP,MCF5206_CS_CSMR1,32,DATA)
#define MCF5206_WR_CS_CSCR1(IMMP,DATA) \
Mcf5206_iowr(IMMP,MCF5206_CS_CSCR1,16,DATA)
#define MCF5206_WR_CS_CSAR2(IMMP,DATA) \
Mcf5206_iowr(IMMP,MCF5206_CS_CSAR2,16,DATA)
#define MCF5206_WR_CS_CSMR2(IMMP,DATA) \
Mcf5206_iowr(IMMP,MCF5206_CS_CSMR2,32,DATA)
#define MCF5206_WR_CS_CSCR2(IMMP,DATA) \
Mcf5206_iowr(IMMP,MCF5206_CS_CSCR2,16,DATA)
#define MCF5206_WR_CS_CSAR3(IMMP,DATA) \
Mcf5206_iowr(IMMP,MCF5206_CS_CSAR3,16,DATA)
#define MCF5206_WR_CS_CSMR3(IMMP,DATA) \
Mcf5206_iowr(IMMP,MCF5206_CS_CSMR3,32,DATA)
#define MCF5206_WR_CS_CSCR3(IMMP,DATA) \
Mcf5206_iowr(IMMP,MCF5206_CS_CSCR3,16,DATA)
#define MCF5206_WR_CS_CSAR4(IMMP,DATA) \
Mcf5206_iowr(IMMP,MCF5206_CS_CSAR4,16,DATA)
#define MCF5206_WR_CS_CSMR4(IMMP,DATA) \
Mcf5206_iowr(IMMP,MCF5206_CS_CSMR4,32,DATA)
#define MCF5206_WR_CS_CSCR4(IMMP,DATA) \
Mcf5206_iowr(IMMP,MCF5206_CS_CSCR4,16,DATA)
#define MCF5206_WR_CS_CSAR5(IMMP,DATA) \
Mcf5206_iowr(IMMP,MCF5206_CS_CSAR5,16,DATA)
#define MCF5206_WR_CS_CSMR5(IMMP,DATA) \
Mcf5206_iowr(IMMP,MCF5206_CS_CSMR5,32,DATA)
#define MCF5206_WR_CS_CSCR5(IMMP,DATA) \
Mcf5206_iowr(IMMP,MCF5206_CS_CSCR5,16,DATA)
#define MCF5206_WR_CS_CSAR6(IMMP,DATA) \
Mcf5206_iowr(IMMP,MCF5206_CS_CSAR6,16,DATA)
#define MCF5206_WR_CS_CSMR6(IMMP,DATA) \
Mcf5206_iowr(IMMP,MCF5206_CS_CSMR6,32,DATA)
#define MCF5206_WR_CS_CSCR6(IMMP,DATA) \
Mcf5206_iowr(IMMP,MCF5206_CS_CSCR6,16,DATA)
#define MCF5206_WR_CS_CSAR7(IMMP,DATA) \
Mcf5206_iowr(IMMP,MCF5206_CS_CSAR7,16,DATA)
#define MCF5206_WR_CS_CSMR7(IMMP,DATA) \
Mcf5206_iowr(IMMP,MCF5206_CS_CSMR7,32,DATA)
#define MCF5206_WR_CS_CSCR7(IMMP,DATA) \
Mcf5206_iowr(IMMP,MCF5206_CS_CSCR7,16,DATA)
#define MCF5206_WR_CS_DMCR(IMMP,DATA) \
Mcf5206_iowr(IMMP,MCF5206_CS_DMCR,16,DATA)
#if 1
typedef volatile struct
{
uint32 reserved1[0x19];
uint16 CSAR0;
uint16 reservdA;
uint32 CSMR0;
uint16 reserved2;
uint16 CSCR0;
uint16 CSAR1;
uint16 reservdB;
uint32 CSMR1;
uint16 reserved4;
uint16 CSCR1;
uint16 CSAR2;
uint16 reservdC;
uint32 CSMR2;
uint16 reserved6;
uint16 CSCR2;
uint16 CSAR3;
uint16 reservdD;
uint32 CSMR3;
uint16 reserved8;
uint16 CSCR3;
uint16 CSAR4;
uint16 reservdE;
uint32 CSMR4;
uint16 reserved10;
uint16 CSCR4;
uint16 CSAR5;
uint16 reservdF;
uint32 CSMR5;
uint16 reserved12;
uint16 CSCR5;
uint16 CSAR6;
uint16 reservdG;
uint32 CSMR6;
uint16 reserved14;
uint16 CSCR6;
uint16 CSAR7;
uint16 reservdH;
uint32 CSMR7;
uint16 reserved16;
uint16 CSCR7;
uint16 reserved17;
uint16 DMCR;
} MCF5206_CS;
#endif
#define MCF5206_CS_CSAR_BASE(a) (((a)&0xFFFF0000)>>16)
#define MCF5206_CS_CSMR_MASK_32M (0x01FF0000)
#define MCF5206_CS_CSMR_MASK_16M (0x00FF0000)
#define MCF5206_CS_CSMR_MASK_8M (0x007F0000)
#define MCF5206_CS_CSMR_MASK_4M (0x003F0000)
#define MCF5206_CS_CSMR_MASK_2M (0x001F0000)
#define MCF5206_CS_CSMR_MASK_1M (0x000F0000)
#define MCF5206_CS_CSMR_MASK_1024K (0x000F0000)
#define MCF5206_CS_CSMR_MASK_512K (0x00070000)
#define MCF5206_CS_CSMR_MASK_256K (0x00030000)
#define MCF5206_CS_CSMR_MASK_128K (0x00010000)
#define MCF5206_CS_CSMR_MASK_64K (0x00000000)
#define MCF5206_CS_CSMR_SC (0x00000010)
#define MCF5206_CS_CSMR_SD (0x00000008)
#define MCF5206_CS_CSMR_UC (0x00000004)
#define MCF5206_CS_CSMR_UD (0x00000002)
#define MCF5206_CS_CSMR1_CPU (0x00000020)
#define MCF5206_CS_CSCR_WS_MASK (0x3C00)
#define MCF5206_CS_CSCR_WS(a) (((a)&0x0F)<<10)
#define MCF5206_CS_CSCR_BRST (0x0200)
#define MCF5206_CS_CSCR_AA (0x0100)
#define MCF5206_CS_CSCR_PS_8 (0x0040)
#define MCF5206_CS_CSCR_PS_16 (0x0080)
#define MCF5206_CS_CSCR_PS_32 (0x0000)
#define MCF5206_CS_CSCR_EMAA (0x0020)
#define MCF5206_CS_CSCR_ASET (0x0010)
#define MCF5206_CS_CSCR_WRAH (0x0008)
#define MCF5206_CS_CSCR_RDAH (0x0004)
#define MCF5206_CS_CSCR_WR (0x0002)
#define MCF5206_CS_CSCR_RD (0x0001)
#define MCF5206_CS_DMCR_WS_MASK (0x3C00)
#define MCF5206_CS_DMCR_WS(a) (((a)&0x0F)<<10)
#define MCF5206_CS_DMCR_BRST (0x0200)
#define MCF5206_CS_DMCR_AA (0x0100)
#define MCF5206_CS_DMCR_PS_8 (0x0040)
#define MCF5206_CS_DMCR_PS_16 (0x0080)
#define MCF5206_CS_DMCR_PS_32 (0x0000)
#define MCF5206_CS_DMCR_EMAA (0x0020)
#define MCF5206_CS_DMCR_WRAH (0x0008)
#define MCF5206_CS_DMCR_RDAH (0x0004)
#define MCF5206_IACK_ADDRESS (MCF5206_CS_CSAR_BASE(0xFFFFFFE0))
#define MCF5206_IACK_MASK (MCF5206_CS_CSMR_MASK_64K)
/***********************************************************************/
/*
* Parallel Port (General Purpose I/O) Module, PP
*/
/* Offsets of the registers from the MBAR */
#define MCF5206_PP_PPDDR (0x01C5)
#define MCF5206_PP_PPDAT (0x01C9)
/* Read access macros for general use */
#define MCF5206_RD_PP_PPDDR(IMMP) Mcf5206_iord(IMMP,MCF5206_PP_PPDDR,8)
#define MCF5206_RD_PP_PPDAT(IMMP) Mcf5206_iord(IMMP,MCF5206_PP_PPDAT,8)
/* Write access macros for general use */
#define MCF5206_WR_PP_PPDDR(IMMP,DATA) \
Mcf5206_iowr(IMMP,MCF5206_PP_PPDDR,8,DATA)
#define MCF5206_WR_PP_PPDAT(IMMP,DATA) \
Mcf5206_iowr(IMMP,MCF5206_PP_PPDAT,8,DATA)
#if 1
typedef volatile struct
{
uint8 reserved0[0x1C5];
uint8 PPDDR;
uint8 reserved34;
uint8 reserved35;
uint8 reserved36;
uint8 PPDAT;
} MCF5206_PP;
#endif
#define MCF5206_PP_PPDDR_DDR7 (0x80)
#define MCF5206_PP_PPDDR_DDR6 (0x40)
#define MCF5206_PP_PPDDR_DDR5 (0x20)
#define MCF5206_PP_PPDDR_DDR4 (0x10)
#define MCF5206_PP_PPDDR_DDR3 (0x08)
#define MCF5206_PP_PPDDR_DDR2 (0x04)
#define MCF5206_PP_PPDDR_DDR1 (0x02)
#define MCF5206_PP_PPDDR_DDR0 (0x01)
#define MCF5206_PP_PPDDR_DDR7_INPUT (~0x80)
#define MCF5206_PP_PPDDR_DDR7_OUTPUT ( 0x80)
#define MCF5206_PP_PPDDR_DDR6_INPUT (~0x40)
#define MCF5206_PP_PPDDR_DDR6_OUTPUT ( 0x40)
#define MCF5206_PP_PPDDR_DDR5_INPUT (~0x20)
#define MCF5206_PP_PPDDR_DDR5_OUTPUT ( 0x20)
#define MCF5206_PP_PPDDR_DDR4_INPUT (~0x10)
#define MCF5206_PP_PPDDR_DDR4_OUTPUT ( 0x10)
#define MCF5206_PP_PPDDR_DDR3_INPUT (~0x08)
#define MCF5206_PP_PPDDR_DDR3_OUTPUT ( 0x08)
#define MCF5206_PP_PPDDR_DDR2_INPUT (~0x04)
#define MCF5206_PP_PPDDR_DDR2_OUTPUT ( 0x04)
#define MCF5206_PP_PPDDR_DDR1_INPUT (~0x02)
#define MCF5206_PP_PPDDR_DDR1_OUTPUT ( 0x02)
#define MCF5206_PP_PPDDR_DDR0_INPUT (~0x01)
#define MCF5206_PP_PPDDR_DDR0_OUTPUT ( 0x01)
#define MCF5206_PP_PPDAT_DAT7 (0x80)
#define MCF5206_PP_PPDAT_DAT6 (0x40)
#define MCF5206_PP_PPDAT_DAT5 (0x20)
#define MCF5206_PP_PPDAT_DAT4 (0x10)
#define MCF5206_PP_PPDAT_DAT3 (0x08)
#define MCF5206_PP_PPDAT_DAT2 (0x04)
#define MCF5206_PP_PPDAT_DAT1 (0x02)
#define MCF5206_PP_PPDAT_DAT0 (0x01)
/***********************************************************************/
/*
* DRAM Controller Module, DRAMC
*/
/* Offsets of the registers from the MBAR */
#define MCF5206_DRAMC_DCRR (0x0046)
#define MCF5206_DRAMC_DCTR (0x004A)
#define MCF5206_DRAMC_DCAR0 (0x004C)
#define MCF5206_DRAMC_DCMR0 (0x0050)
#define MCF5206_DRAMC_DCCR0 (0x0057)
#define MCF5206_DRAMC_DCAR1 (0x0058)
#define MCF5206_DRAMC_DCMR1 (0x005C)
#define MCF5206_DRAMC_DCCR1 (0x0063)
/* Read access macros for general use */
#define MCF5206_RD_DRAMC_DCRR(IMMP) \
Mcf5206_iord(IMMP,MCF5206_DRAMC_DCRR,16)
#define MCF5206_RD_DRAMC_DCTR(IMMP) \
Mcf5206_iord(IMMP,MCF5206_DRAMC_DCTR,16)
#define MCF5206_RD_DRAMC_DCAR0(IMMP) \
Mcf5206_iord(IMMP,MCF5206_DRAMC_DCAR0,16)
#define MCF5206_RD_DRAMC_DCMR0(IMMP) \
Mcf5206_iord(IMMP,MCF5206_DRAMC_DCMR0,32)
#define MCF5206_RD_DRAMC_DCCR0(IMMP) \
Mcf5206_iord(IMMP,MCF5206_DRAMC_DCCR0,8)
#define MCF5206_RD_DRAMC_DCAR1(IMMP) \
Mcf5206_iord(IMMP,MCF5206_DRAMC_DCAR1,16)
#define MCF5206_RD_DRAMC_DCMR1(IMMP) \
Mcf5206_iord(IMMP,MCF5206_DRAMC_DCMR1,32)
#define MCF5206_RD_DRAMC_DCCR1(IMMP) \
Mcf5206_iord(IMMP,MCF5206_DRAMC_DCCR1,8)
/* Write access macros for general use */
#define MCF5206_WR_DRAMC_DCRR(IMMP,DATA) \
Mcf5206_iowr(IMMP,MCF5206_DRAMC_DCRR,16,DATA)
#define MCF5206_WR_DRAMC_DCTR(IMMP,DATA) \
Mcf5206_iowr(IMMP,MCF5206_DRAMC_DCTR,16,DATA)
#define MCF5206_WR_DRAMC_DCAR0(IMMP,DATA) \
Mcf5206_iowr(IMMP,MCF5206_DRAMC_DCAR0,16,DATA)
#define MCF5206_WR_DRAMC_DCMR0(IMMP,DATA) \
Mcf5206_iowr(IMMP,MCF5206_DRAMC_DCMR0,32,DATA)
#define MCF5206_WR_DRAMC_DCCR0(IMMP,DATA) \
Mcf5206_iowr(IMMP,MCF5206_DRAMC_DCCR0,8,DATA)
#define MCF5206_WR_DRAMC_DCAR1(IMMP,DATA) \
Mcf5206_iowr(IMMP,MCF5206_DRAMC_DCAR1,16,DATA)
#define MCF5206_WR_DRAMC_DCMR1(IMMP,DATA) \
Mcf5206_iowr(IMMP,MCF5206_DRAMC_DCMR1,32,DATA)
#define MCF5206_WR_DRAMC_DCCR1(IMMP,DATA) \
Mcf5206_iowr(IMMP,MCF5206_DRAMC_DCCR1,8,DATA)
#if 1
typedef volatile struct
{
uint16 reserved1[0x23];
uint16 DCRR;
uint16 reserved2;
uint16 DCTR;
uint16 DCAR0;
uint16 reserved4;
uint32 DCMR0;
uint8 reserved5[3];
uint8 DCCR0;
uint16 DCAR1;
uint16 reserved6;
uint32 DCMR1;
uint8 reserved7[3];
uint8 DCCR1;
} MCF5206_DRAMC;
#endif
#define MCF5206_DRAMC_DCRR_RC(a) ((a)&0x0FFF)
#define MCF5206_DRAMC_DCTR_DAEM (0x8000)
#define MCF5206_DRAMC_DCTR_EDO (0x4000)
#define MCF5206_DRAMC_DCTR_RCD (0x1000)
#define MCF5206_DRAMC_DCTR_RSH_1 (0x0000)
#define MCF5206_DRAMC_DCTR_RSH_2 (0x0200)
#define MCF5206_DRAMC_DCTR_RSH_3 (0x0400)
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