layer0.sro

用vhdl编写的FFT的代码,很全,很强大.

# Created by Synplify Verilog HDL Compiler version 3.4.1, Build 079R from Synplicity, Inc.
# Copyright 1994-2004 Synplicity, Inc. , All rights reserved.
# Synthesis Netlist written on Tue Sep 05 14:27:12 2006
#
#
#OPTIONS:"|-mixedhdl|-modhint|_verilog_hintfile|-top|fft_test|-layerid|0|-primux|-fixsmult|-sdff_counter|-infer_seqShift|-nram|-divnmod|-I|D:\\Develop\\PQS\\FPGA\\fft_test\\|-I|C:\\Program Files\\Synplicity\\fpga_85\\lib|-v2001|-devicelib|C:\\Program Files\\Synplicity\\fpga_85\\lib\\xilinx\\unisim.v|-autosm|-fid2|-sharing|on|-encrypt|-ui|-pro|-ram|-ll|2000"
#CUR:"C:\\Program Files\\Synplicity\\fpga_85\\bin\\c_ver.exe":1141193542
#CUR:"_verilog_hintfile":1157436852
#CUR:"C:\\Program Files\\Synplicity\\fpga_85\\lib\\xilinx\\unisim.v":1141134798
#CUR:"C:\\Program Files\\Synplicity\\fpga_85\\lib\\xilinx\\unisim.v":1141134798
#CUR:"C:\\Program Files\\Synplicity\\fpga_85\\bin\\..\\lib\\xilinx\\unisim.v":1141134798
#CUR:"C:\\Program Files\\Synplicity\\fpga_85\\bin\\..\\lib\\xilinx\\unisim.v":1141134798
#CUR:"D:\\Develop\\PQS\\FPGA\\fft_test\\fft_test.v":1157437626
#CUR:"D:\\Develop\\PQS\\FPGA\\fft_test\\fft_test.v":1157437626
f "C:\Program Files\Synplicity\fpga_85\lib\xilinx\unisim.v"; # file 0
af .is_verilog 1;
f "C:\Program Files\Synplicity\fpga_85\bin\..\lib\xilinx\unisim.v"; # file 1
af .is_verilog 1;
f "D:\Develop\PQS\FPGA\fft_test\fft_test.v"; # file 2
af .is_verilog 1;
@E
@ 
ftell;
@E@MR@U.:(::cU6(:RsIF	NRslCRPsFHDoN;
PCR3Gs0CMRND4N;
PHR3#sPCHoDFR
4;N3PRHP#_CDsHF4oR;P
NRs3FHNohl"CRs"Nl;P
NR$3#MN_VLOsHN80CR
4;
@HR@U.:(::cU6(:R8N8s:rnjN9R8r8sn9:j;



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@HR@U.:(::cU6(:RM8Hr:46j89RH4Mr69:j;



@FR@U.:(::cU6(:Rk8F06r4:Rj980Fkr:46j
9;
@HR@U.:(::cU6(:RRICI
C;b@R@.(:U:Uc:(R:688ORFrk04j6:9FR8k40r69:j;H
NR$3#MN_VLOsHN80C_MbHR
4;@
 

ftell;
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PCR3Gs0CMRND4N;
PHR3#sPCHoDFR
4;N3PRHP#_CDsHF4oR;P
NRs3FHNohl"CRV"V0;P
NR$3#MN_VLOsHN80CR
4;
@HR@n.:(::cn6(:R8VI_PHM_RICV_I8H_MPI
C;
@FR@n.:(::cn6(:R8sVR8sV;



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8;
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b@:@.nc(:::n(6OR8R_G	HCM8G:rnjG9R	M_H8rCGn9:j;H
NR$3#MN_VLOsHN80C_MbHR
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9;N3HR#_$MVsNLH0ONCb8_H4MR;R
b@:@.nc(:::n(6OR8R_GMHCM8G:rnjG9RMM_H8rCGn9:j;H
NR$3#MN_VLOsHN80C_MbHR
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9;N3HR#_$MVsNLH0ONCb8_H4MR;R
b@:@.nc(:::n(6OR8RFC8MCCR8CFM;H
NR$3#MN_VLOsHN80C_MbHR
4;b@R@.(:n:nc:(R:68LORkR#$L$k#;H
NR$3#MN_VLOsHN80C_MbHR
4;b@R@.(:n:nc:(R:688ORFRMC8CFM;H
NR$3#MN_VLOsHN80C_MbHR
4;b@R@.(:n:nc:(R:688ORPPR8;H
NR$3#MN_VLOsHN80C_MbHR
4;b@R@.(:n:nc:(R:68sORVs8RV
8;N3HR#_$MVsNLH0ONCb8_H4MR; 
@
ftell;
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RNP3PH#CDsHF4oR;P
NR#3H_sPCHoDFR
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9;
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9;
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9;
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9;
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8;
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9;
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9;
@FR@c.:c(:4::cc4LgRDc	r:Rj9LrD	c9:j;



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0;
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9;s@R@.(:n:nc:(R:6I	FsR0VVRsPCHoDFR
k4S8VI_PHM_=IC0Csk
VSs8V=s8#
S00Ns=N#0sS0
V_I8H=MP0Csk
PS8=
8PSDkMF=N88CFM
FS8M8C=F
MCS	OD=	OD
kSL#L$=k
#$SFC8MCC=8CFM
MSG_rsC4j6:9M=G_rsC4j6:9L
SDC	_Gcbr:=j9LrD	c9:j
	SG_rHl4j6:9	=G_rHl4j6:9G
SMM_H8rCGn9:j=_GMHCM8G:rnjS9
Gs	_C6r4:=j9Gs	_C6r4:
j9S_GMH4lr69:j=_GMH4lr69:j
	SG_8HMCnGr:=j9GH	_MG8Crjn:9s;
R.@@::U(c(:U:I6RFRs	sRNlPHCsDRFokS.
Ns88rjn:9N=sl8_N8nsr:
j9S	OD=	OD
HS8M6r4:=j9V#NDCN,VD,#CV#NDCN,VD,#CV#NDCN,VD,#CV#NDCN,VD,#CV#NDCN,VD,#CV#NDCN,VD,#CV#NDCN,VD,#CV#NDCN,VD
#CSk8F06r4:=j9GsM_C6r4:
j9S=ICV#NDCb;
Rj@@:44::.4:Rk0sCsR0k0CRs;kC
@bR@4j::44::V.RNCD#RDVN#VCRNCD#;R
b@:@.gjn:::gn6VR8VssRVR84s4V8R8sVR	ODR#sCC
0;N3HR#_$MbOsFMCNlRs"bFsO_V"84;H
NR03sDs_FHNoMl"CRs4V8"b;
R.@@:.44:4.:4d.:R8N8RlsN_8N8sr_cn9:jRlsN_8N8sr_cn9:jRlsN_8N8s:rnjs9RV;84
@bR@4.:jj(::(4j:86RVRV#s_NlNs88rjn:9NRsl8_N8nsr:Rj9s_NlNs88_ncr:Rj9ORD	sCC#0N;
H#R3$bM_sMFONRlC"FbsON_sl8_N8;s"
RNH3Ds0_HFsolMNCsR"NNl_8"8s;