📄 fft_wave.tbw
字号:
version 3
D:/Develop/PQS/FPGA/fft_test/fft_test.v
fft_test
VERILOG
VERILOG
fft_wave.xwv
Clocked
-
-
1000000000
ns
GSR:true
PRLD:false
100000000
CLOCK_LIST_BEGIN
clk
10000000
10000000
2000000
2000000
100000000
RISING
CLOCK_LIST_END
SIGNAL_LIST_BEGIN
blk
clk
done
clk
ram_addr
clk
reset
clk
rfd
clk
start
clk
xk_im
clk
xk_index
clk
xk_re
clk
xn_im
clk
xn_index
clk
xn_re
clk
SIGNAL_LIST_END
SIGNALS_NOT_ON_DISPLAY
blk_DIFF
done_DIFF
ram_addr_DIFF
rfd_DIFF
xk_im_DIFF
xk_index_DIFF
xk_re_DIFF
xn_index_DIFF
xn_re_DIFF
SIGNALS_NOT_ON_DISPLAY_END
MARKER_LIST_BEGIN
MARKER_LIST_END
MEASURE_LIST_BEGIN
MEASURE_LIST_END
SIGNAL_ORDER_BEGIN
clk
reset
start
xn_im
done
rfd
blk
xk_im
xk_index
xk_re
xn_index
xn_re
ram_addr
SIGNAL_ORDER_END
-X-X-X-
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