coregen.xml

来自「用vhdl编写的FFT的代码,很全,很强大.」· XML 代码 · 共 205 行

<?xml version="1.0" encoding="UTF-8"?>
<RootFolder label="COREGEN" treetype="folder" language="COREGEN">
	<Folder label="VERILOG Component Instantiation" treetype="folder">
		<Template label="fft_128" treetype="template">
 
 
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
 
fft_128 YourInstanceName (
    .xn_re(xn_re),
    .xn_im(xn_im),
    .start(start),
    .unload(unload),
    .fwd_inv(fwd_inv),
    .fwd_inv_we(fwd_inv_we),
    .clk(clk),
    .xk_re(xk_re),
    .xk_im(xk_im),
    .xn_index(xn_index),
    .xk_index(xk_index),
    .rfd(rfd),
    .busy(busy),
    .dv(dv),
    .edone(edone),
    .done(done),
    .blk_exp(blk_exp));

 
		</Template>
		<Template label="fft" treetype="template">
 
 
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
 
fft YourInstanceName (
    .xn_re(xn_re),
    .xn_im(xn_im),
    .start(start),
    .unload(unload),
    .fwd_inv(fwd_inv),
    .fwd_inv_we(fwd_inv_we),
    .clk(clk),
    .xk_re(xk_re),
    .xk_im(xk_im),
    .xn_index(xn_index),
    .xk_index(xk_index),
    .rfd(rfd),
    .busy(busy),
    .dv(dv),
    .edone(edone),
    .done(done),
    .blk_exp(blk_exp));

 
		</Template>
		<Template label="ram" treetype="template">
		</Template>
	</Folder>
	<Folder label="VHDL Component Instantiation" treetype="folder">
		<Template label="fft_128" treetype="template">
 
 
-- The following code must appear in the VHDL architecture header:
 
component fft_128
    port (
    xn_re: IN std_logic_VECTOR(15 downto 0);
    xn_im: IN std_logic_VECTOR(15 downto 0);
    start: IN std_logic;
    unload: IN std_logic;
    fwd_inv: IN std_logic;
    fwd_inv_we: IN std_logic;
    clk: IN std_logic;
    xk_re: OUT std_logic_VECTOR(15 downto 0);
    xk_im: OUT std_logic_VECTOR(15 downto 0);
    xn_index: OUT std_logic_VECTOR(6 downto 0);
    xk_index: OUT std_logic_VECTOR(6 downto 0);
    rfd: OUT std_logic;
    busy: OUT std_logic;
    dv: OUT std_logic;
    edone: OUT std_logic;
    done: OUT std_logic;
    blk_exp: OUT std_logic_VECTOR(4 downto 0));
end component;



 
-------------------------------------------------------------
 
-- The following code must appear in the VHDL architecture body.
-- Substitute your own instance name and net names.
 
your_instance_name : fft_128
        port map (
            xn_re =&gt; xn_re,
            xn_im =&gt; xn_im,
            start =&gt; start,
            unload =&gt; unload,
            fwd_inv =&gt; fwd_inv,
            fwd_inv_we =&gt; fwd_inv_we,
            clk =&gt; clk,
            xk_re =&gt; xk_re,
            xk_im =&gt; xk_im,
            xn_index =&gt; xn_index,
            xk_index =&gt; xk_index,
            rfd =&gt; rfd,
            busy =&gt; busy,
            dv =&gt; dv,
            edone =&gt; edone,
            done =&gt; done,
            blk_exp =&gt; blk_exp);
 
		</Template>
		<Template label="fft" treetype="template">
 
 
-- The following code must appear in the VHDL architecture header:
 
component fft
    port (
    xn_re: IN std_logic_VECTOR(15 downto 0);
    xn_im: IN std_logic_VECTOR(15 downto 0);
    start: IN std_logic;
    unload: IN std_logic;
    fwd_inv: IN std_logic;
    fwd_inv_we: IN std_logic;
    clk: IN std_logic;
    xk_re: OUT std_logic_VECTOR(15 downto 0);
    xk_im: OUT std_logic_VECTOR(15 downto 0);
    xn_index: OUT std_logic_VECTOR(6 downto 0);
    xk_index: OUT std_logic_VECTOR(6 downto 0);
    rfd: OUT std_logic;
    busy: OUT std_logic;
    dv: OUT std_logic;
    edone: OUT std_logic;
    done: OUT std_logic;
    blk_exp: OUT std_logic_VECTOR(4 downto 0));
end component;



 
-------------------------------------------------------------
 
-- The following code must appear in the VHDL architecture body.
-- Substitute your own instance name and net names.
 
your_instance_name : fft
        port map (
            xn_re =&gt; xn_re,
            xn_im =&gt; xn_im,
            start =&gt; start,
            unload =&gt; unload,
            fwd_inv =&gt; fwd_inv,
            fwd_inv_we =&gt; fwd_inv_we,
            clk =&gt; clk,
            xk_re =&gt; xk_re,
            xk_im =&gt; xk_im,
            xn_index =&gt; xn_index,
            xk_index =&gt; xk_index,
            rfd =&gt; rfd,
            busy =&gt; busy,
            dv =&gt; dv,
            edone =&gt; edone,
            done =&gt; done,
            blk_exp =&gt; blk_exp);
 
		</Template>
		<Template label="ram" treetype="template">
 
 
-- The following code must appear in the VHDL architecture header:
 
component ram
    port (
    addr: IN std_logic_VECTOR(6 downto 0);
    clk: IN std_logic;
    din: IN std_logic_VECTOR(15 downto 0);
    dout: OUT std_logic_VECTOR(15 downto 0);
    we: IN std_logic);
end component;

 
-------------------------------------------------------------
 
-- The following code must appear in the VHDL architecture body.
-- Substitute your own instance name and net names.
 
your_instance_name : ram
        port map (
            addr =&gt; addr,
            clk =&gt; clk,
            din =&gt; din,
            dout =&gt; dout,
            we =&gt; we);
 
		</Template>
	</Folder>
</RootFolder>