fft_test_bb.v

来自「用vhdl编写的FFT的代码,很全,很强大.」· Verilog 代码 · 共 29 行

module fft (fwd_inv_we,rfd,start,fwd_inv,dv,unload,done,clk,busy,edone,xn_re,blk_exp,xk_im,xn_index,xk_re,xn_im,xk_index);
input fwd_inv_we;
output rfd;
input start;
input fwd_inv;
output dv;
input unload;
output done;
input clk;
output busy;
output edone;
input [15:0]xn_re;
output [4:0]blk_exp;
output [15:0]xk_im;
output [6:0]xn_index;
output [15:0]xk_re;
input [15:0]xn_im;
output [6:0]xk_index;
endmodule

module ram (addr,clk,din,dout,we);
input [6:0]addr;
input clk;
input [15:0]din;
output [15:0]dout;
input we;
endmodule