fft_test.v

来自「用vhdl编写的FFT的代码,很全,很强大.」· Verilog 代码 · 共 120 行

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    14:06:02 08/12/2006 
// Design Name: 
// Module Name:    fft_test 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module fft_test(
				clk, 
				reset, 
				xn_re, 
				xn_im, 
				xn_index,
				ram_addr,				
				rfd, 
				xk_re, 
				xk_im, 
				blk, 
				start, 
				done,
				xk_index
);
    input 			clk;
    input 			reset;
    output[15:0] 	xn_re;
    input[15:0] 	xn_im;
    output[6:0] 	xn_index,ram_addr;
    output 			rfd;
    output[15:0] 	xk_re;
    output[15:0] 	xk_im;
    output[4:0] 	blk;
    input 			start;
    output 			done;
	 output[6:0]	xk_index;

/////////////////////////////////////////////////////////////////

wire 			clk;
wire 			reset;
wire[15:0] 	xn_re,xn_im;
wire[6:0] 	xn_index;
wire 			rfd;
wire[15:0] 	xk_re,xk_im;
wire[4:0] 	blk;
wire 			start;
wire 			done;
wire[6:0]	xk_index;
wire 			dv;
wire[15:0]	din;

reg[6:0]		ram_addr;
reg			rfd1;

fft u1(
  .fwd_inv_we(1'b1),
  .rfd(rfd),
  .start(start),
  .fwd_inv(1'b1),
  .dv(dv),
  .unload(done),
  .done(done),
  .clk(clk),
  .busy(busy),
  .edone(edone),
  .xn_re(xn_re),
  .blk_exp(blk),
  .xk_im(xk_im),
  .xn_index(xn_index),
  .xk_re(xk_re),
  .xn_im(xn_im),
  .xk_index(xk_index)
);

ram u2(
	.addr(ram_addr),
	.clk(clk),
	.din(din),
	.dout(xn_re),
	.we(1'b0)
);	

//genreate 4 clock delay after xn_index
always @(posedge clk or posedge reset)
begin
	if (reset) begin
		rfd1 <= 0;
	end else begin
		rfd1 <= rfd;
	end
end


//grnerate rd_ram_addr
always @(posedge clk or posedge reset)
begin
	if (reset) begin
		ram_addr <= 127;
	end else begin
		if (rfd1) begin //xn_re input delay from rfd1~rfd3
			ram_addr <= ram_addr + 1;
		end
	end
end


endmodule