layer1.tlg

来自「用vhdl编写的FFT的代码,很全,很强大.」· TLG 代码 · 共 7 行

@N: CD630 :"D:\Develop\PQS\FPGA\fft_test\fft.vhd":48:7:48:9|Synthesizing work.fft.structure 
@W: CD286 :"D:\Develop\PQS\FPGA\fft_test\fft.vhd":48:7:48:9|Creating black box for empty architecture fft 
Post processing for work.fft.structure
@N: CD630 :"D:\Develop\PQS\FPGA\fft_test\ram.vhd":43:7:43:9|Synthesizing work.ram.ram_a 
@W: CD286 :"D:\Develop\PQS\FPGA\fft_test\ram.vhd":43:7:43:9|Creating black box for empty architecture ram 
Post processing for work.ram.ram_a