fft_test_core.cgp

来自「用vhdl编写的FFT的代码,很全,很强大.」· CGP 代码 · 共 21 行

# Date: Tue Sep 05 06:07:42 2006
SET flowvendor = Other
SET vhdlsim = True
SET verilogsim = False
SET workingdirectory = D:\Develop\PQS\FPGA\fft_test\fft_test_core\tmp
SET speedgrade = -5
SET simulationfiles = Behavioral
SET asysymbol = False
SET addpads = False
SET device = xc3s500e
SET implementationfiletype = Edif
SET busformat = BusFormatAngleBracketNotRipped
SET foundationsym = False
SET package = cp132
SET createndf = False
SET designentry = VHDL
SET devicefamily = spartan3e
SET formalverification = False
SET removerpms = False