layer0.tlg

来自「用vhdl编写的FFT的代码,很全,很强大.」· TLG 代码 · 共 6 行

@N: CG364 :"D:\Develop\PQS\FPGA\fft_test\fft_test.v":21:7:21:14|Synthesizing module fft_test

@W: CG360 :"D:\Develop\PQS\FPGA\fft_test\fft_test.v":62:11:62:13|No assignment to wire din

@W: CL156 :"D:\Develop\PQS\FPGA\fft_test\fft_test.v":87:4:87:5|*Input din[15:0] to this expression [instance] has undriven bits which are being tied to 0 - a simulation mismatch is possible