📄 fft_test_srr.htm
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@I::"C:\Program Files\Synplicity\fpga_85\lib\xilinx\unisim.v"
@I::"C:\Program Files\Synplicity\fpga_85\bin\..\lib\xilinx\unisim.v"
@I::"D:\Develop\PQS\FPGA\fft_test\fft_test.v"
Verilog syntax check successful!
File D:\Develop\PQS\FPGA\fft_test\fft_test.v changed - recompiling
@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="d:\develop\pqs\fpga\fft_test\fft_test.v:21:7:21:15:@N:CG364:@XP_MSG">fft_test.v(21)</a><!@TM:1157437633> | Synthesizing module fft_test
<font color=#A52A2A>@W:<a href="@W:CG360:@XP_HELP">CG360</a> : <a href="d:\develop\pqs\fpga\fft_test\fft_test.v:62:11:62:14:@W:CG360:@XP_MSG">fft_test.v(62)</a><!@TM:1157437633> | No assignment to wire din</font>
<font color=#A52A2A>@W:<a href="@W:CL156:@XP_HELP">CL156</a> : <a href="d:\develop\pqs\fpga\fft_test\fft_test.v:87:4:87:6:@W:CL156:@XP_MSG">fft_test.v(87)</a><!@TM:1157437633> | *Input din[15:0] to this expression [instance] has undriven bits which are being tied to 0 - a simulation mismatch is possible</font>
# Tue Sep 05 14:27:12 2006
@I:: "D:\Develop\PQS\FPGA\fft_test\ram.vhd"
@I:: "D:\Develop\PQS\FPGA\fft_test\fft.vhd"
VHDL syntax check successful!
@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="d:\develop\pqs\fpga\fft_test\fft.vhd:48:7:48:10:@N:CD630:@XP_MSG">fft.vhd(48)</a><!@TM:1157437633> | Synthesizing work.fft.structure
<font color=#A52A2A>@W:<a href="@W:CD286:@XP_HELP">CD286</a> : <a href="d:\develop\pqs\fpga\fft_test\fft.vhd:48:7:48:10:@W:CD286:@XP_MSG">fft.vhd(48)</a><!@TM:1157437633> | Creating black box for empty architecture fft </font>
Post processing for work.fft.structure
@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="d:\develop\pqs\fpga\fft_test\ram.vhd:43:7:43:10:@N:CD630:@XP_MSG">ram.vhd(43)</a><!@TM:1157437633> | Synthesizing work.ram.ram_a
<font color=#A52A2A>@W:<a href="@W:CD286:@XP_HELP">CD286</a> : <a href="d:\develop\pqs\fpga\fft_test\ram.vhd:43:7:43:10:@W:CD286:@XP_MSG">ram.vhd(43)</a><!@TM:1157437633> | Creating black box for empty architecture ram </font>
Post processing for work.ram.ram_a
# Tue Sep 05 14:27:12 2006
Synplicity Netlist Filter, version 3.4.1, Build 079R, built Mar 1 2006
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Tue Sep 05 14:27:13 2006
@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Tue Sep 05 14:27:13 2006
###########################################################[
<a name=mapperReport3>Synplicity Xilinx Technology Mapper, Version 8.4.0.p, Build 081R, Built Mar 11 2006
Copyright (C) 1994-2006, Synplicity Inc. All Rights Reserved
Version 8.5
Reading constraint file: D:\Develop\PQS\FPGA\fft_test\fft_test.sdc
@N:<a href="@N:MF249:@XP_HELP">MF249</a> : <!@TM:1157437635> | Running in 32-bit mode.
@N: : <!@TM:1157437635> | Gated clock conversion disabled
Reading Xilinx I/O pad type table from file <C:\Program Files\Synplicity\fpga_85\lib/xilinx/x_io_tbl.txt>
Reading Xilinx Rocket I/O parameter type table from file <C:\Program Files\Synplicity\fpga_85\lib/xilinx/gttype.txt>
@N:<a href="@N:MT206:@XP_HELP">MT206</a> : <!@TM:1157437635> | Autoconstrain Mode is ON
RTL optimization done.
Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 30MB)
@N: : <a href="d:\develop\pqs\fpga\fft_test\fft_test.v:107:0:107:6:@N::@XP_MSG">fft_test.v(107)</a><!@TM:1157437635> | Found counter in view:work.fft_test(verilog) inst ram_addr[6:0]
Finished factoring (Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 30MB)
Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 30MB)
Clock Buffers:
Inserting Clock buffer for port clk, TNM=clk
Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 31MB)
Starting Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 31MB)
Finished Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 31MB)
Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 31MB)
Finished preparing to map (Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 31MB)
Finished technology mapping (Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 31MB)
Pass CPU time Worst Slack Luts / Registers
------------------------------------------------------------
1 0h:00m:00s -0.90ns 7 / 8
2 0h:00m:00s -0.90ns 7 / 8
3 0h:00m:00s -0.90ns 7 / 8
------------------------------------------------------------
Timing driven replication report
No replication required.
Timing driven replication report
No replication required.
Timing driven replication report
No replication required.
Timing driven replication report
No replication required.
xct_reducefodelay set to FALSE
Timing driven replication report
No replication required.
Pass CPU time Worst Slack Luts / Registers
------------------------------------------------------------
1 0h:00m:00s -1.23ns 7 / 8
2 0h:00m:00s -1.23ns 7 / 8
3 0h:00m:00s -1.23ns 7 / 8
Timing driven replication report
No replication required.
4 0h:00m:00s -1.23ns 7 / 8
5 0h:00m:00s -1.23ns 7 / 8
6 0h:00m:00s -1.23ns 7 / 8
------------------------------------------------------------
Timing driven replication report
No replication required.
Pass CPU time Worst Slack Luts / Registers
------------------------------------------------------------
1 0h:00m:00s -0.77ns 7 / 8
2 0h:00m:00s -0.77ns 7 / 8
3 0h:00m:00s -0.77ns 7 / 8
Timing driven replication report
No replication required.
------------------------------------------------------------
Net buffering Report for view:work.fft_test(verilog):
No nets needed buffering.
Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 31MB)
@N:<a href="@N:FX164:@XP_HELP">FX164</a> : <!@TM:1157437635> | The option to pack flops in the IOB has not been specified
Finished restoring hierarchy (Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 31MB)
@N:<a href="@N:BN191:@XP_HELP">BN191</a> : <!@TM:1157437635> | Writing property annotation file D:\Develop\PQS\FPGA\fft_test\fft_test.tap.
Writing Analyst data base D:\Develop\PQS\FPGA\fft_test\fft_test.srm
@N:<a href="@N:BN225:@XP_HELP">BN225</a> : <!@TM:1157437635> | Writing default property annotation file D:\Develop\PQS\FPGA\fft_test\fft_test.map.
Writing EDIF Netlist and constraint files
Version 8.5
Found clock fft_test|clk with period 3.36ns
<font color=#A52A2A>@W:<a href="@W:MT246:@XP_HELP">MT246</a> : <a href="d:\develop\pqs\fpga\fft_test\fft_test.v:87:4:87:6:@W:MT246:@XP_MSG">fft_test.v(87)</a><!@TM:1157437635> | Blackbox ram is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) </font>
<font color=#A52A2A>@W:<a href="@W:MT246:@XP_HELP">MT246</a> : <a href="d:\develop\pqs\fpga\fft_test\fft_test.v:67:4:67:6:@W:MT246:@XP_MSG">fft_test.v(67)</a><!@TM:1157437635> | Blackbox fft is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) </font>
<a name=timingReport4>##### START OF TIMING REPORT #####[
# Timing Report written on Tue Sep 05 14:27:15 2006
#
Top view: fft_test
Requested Frequency: 297.5 MHz
Wire load mode: top
Paths requested: 0
Constraint File(s): D:\Develop\PQS\FPGA\fft_test\fft_test.sdc
@N:<a href="@N:MT195:@XP_HELP">MT195</a> : <!@TM:1157437635> | This timing report estimates place and route data. Please look at the place and route timing report for final timing..
@N:<a href="@N:MT197:@XP_HELP">MT197</a> : <!@TM:11⌨️ 快捷键说明
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