📄 eecadd_4.rpt
字号:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: f:\byron1\neweecadd_4\eecadd_4.rpt
eecadd_4
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 4/ 96( 4%) 0/ 48( 0%) 7/ 48( 14%) 3/16( 18%) 5/16( 31%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\byron1\neweecadd_4\eecadd_4.rpt
eecadd_4
** EQUATIONS **
a0 : INPUT;
a1 : INPUT;
a2 : INPUT;
a3 : INPUT;
b0 : INPUT;
b1 : INPUT;
b2 : INPUT;
b3 : INPUT;
cin : INPUT;
-- Node name is 'bcdout0'
-- Equation name is 'bcdout0', type is output
bcdout0 = _LC2_B14;
-- Node name is 'bcdout1'
-- Equation name is 'bcdout1', type is output
bcdout1 = _LC7_B21;
-- Node name is 'bcdout2'
-- Equation name is 'bcdout2', type is output
bcdout2 = _LC1_B21;
-- Node name is 'bcdout3'
-- Equation name is 'bcdout3', type is output
bcdout3 = _LC4_B21;
-- Node name is 'cout'
-- Equation name is 'cout', type is output
cout = _LC5_B21;
-- Node name is ':103'
-- Equation name is '_LC6_B21', type is buried
_LC6_B21 = LCELL( _EQ001);
_EQ001 = _LC3_B14 & _LC3_B21
# _LC1_B14 & _LC3_B21;
-- Node name is ':204'
-- Equation name is '_LC4_B21', type is buried
_LC4_B21 = LCELL( _EQ002);
_EQ002 = _LC2_B21 & _LC3_B14 & !_LC3_B21
# _LC1_B14 & _LC2_B21 & !_LC3_B21
# !_LC1_B14 & !_LC3_B14 & _LC3_B21;
-- Node name is ':211'
-- Equation name is '_LC1_B21', type is buried
_LC1_B21 = LCELL( _EQ003);
_EQ003 = _LC1_B14 & _LC3_B14 & _LC6_B21
# !_LC1_B14 & !_LC3_B14 & _LC6_B21
# _LC1_B14 & _LC2_B21 & _LC3_B14
# !_LC1_B14 & _LC2_B21 & !_LC3_B14
# _LC1_B14 & !_LC2_B21 & !_LC6_B21;
-- Node name is ':220'
-- Equation name is '_LC7_B21', type is buried
_LC7_B21 = LCELL( _EQ004);
_EQ004 = !_LC3_B14 & _LC6_B21
# !_LC2_B21 & _LC3_B14 & !_LC6_B21
# _LC2_B21 & !_LC3_B14;
-- Node name is ':247'
-- Equation name is '_LC5_B21', type is buried
_LC5_B21 = LCELL( _EQ005);
_EQ005 = _LC2_B21
# _LC6_B21;
-- Node name is ':300'
-- Equation name is '_LC3_B14', type is buried
_LC3_B14 = LCELL( _EQ006);
_EQ006 = !a1 & b1 & !_LC5_B14
# a1 & !b1 & !_LC5_B14
# a1 & b1 & _LC5_B14
# !a1 & !b1 & _LC5_B14;
-- Node name is ':319'
-- Equation name is '_LC6_B14', type is buried
_LC6_B14 = LCELL( _EQ007);
_EQ007 = a1 & _LC5_B14
# a1 & b1
# b1 & _LC5_B14;
-- Node name is ':341'
-- Equation name is '_LC1_B14', type is buried
_LC1_B14 = LCELL( _EQ008);
_EQ008 = !a2 & b2 & !_LC6_B14
# a2 & !b2 & !_LC6_B14
# a2 & b2 & _LC6_B14
# !a2 & !b2 & _LC6_B14;
-- Node name is ':375'
-- Equation name is '_LC4_B14', type is buried
_LC4_B14 = LCELL( _EQ009);
_EQ009 = a2 & _LC6_B14
# a2 & b2
# b2 & _LC6_B14;
-- Node name is ':397'
-- Equation name is '_LC3_B21', type is buried
_LC3_B21 = LCELL( _EQ010);
_EQ010 = !a3 & b3 & !_LC4_B14
# a3 & !b3 & !_LC4_B14
# a3 & b3 & _LC4_B14
# !a3 & !b3 & _LC4_B14;
-- Node name is ':431'
-- Equation name is '_LC2_B21', type is buried
_LC2_B21 = LCELL( _EQ011);
_EQ011 = a3 & _LC4_B14
# a3 & b3
# b3 & _LC4_B14;
-- Node name is ':451'
-- Equation name is '_LC2_B14', type is buried
_LC2_B14 = LCELL( _EQ012);
_EQ012 = !a0 & !b0 & cin
# a0 & !b0 & !cin
# a0 & b0 & cin
# !a0 & b0 & !cin;
-- Node name is ':481'
-- Equation name is '_LC5_B14', type is buried
_LC5_B14 = LCELL( _EQ013);
_EQ013 = a0 & b0
# b0 & cin
# a0 & cin;
Project Information f:\byron1\neweecadd_4\eecadd_4.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 12,878K
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