📄 eecadd_8.rpt
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# _LC2_C12 & !_LC4_C5
# !_LC1_C12 & !_LC2_C12 & _LC4_C5;
-- Node name is '~421~1'
-- Equation name is '~421~1', location is LC4_C2, type is buried.
-- synthesized logic cell
!_LC4_C2 = _LC4_C2~NOT;
_LC4_C2~NOT = LCELL( _EQ011);
_EQ011 = a4 & !b4 & _LC2_C12
# !a4 & b4 & _LC2_C12
# a4 & b4 & !_LC2_C12
# !a4 & !b4 & !_LC2_C12
# !_LC8_C2;
-- Node name is '~421~2'
-- Equation name is '~421~2', location is LC2_C3, type is buried.
-- synthesized logic cell
!_LC2_C3 = _LC2_C3~NOT;
_LC2_C3~NOT = LCELL( _EQ012);
_EQ012 = a6 & !b6 & _LC1_C3
# !a6 & b6 & _LC1_C3
# a6 & b6 & !_LC1_C3
# !a6 & !b6 & !_LC1_C3
# !_LC4_C2;
-- Node name is ':455'
-- Equation name is '_LC8_C9', type is buried
!_LC8_C9 = _LC8_C9~NOT;
_LC8_C9~NOT = LCELL( _EQ013);
_EQ013 = !a7 & !b7 & !_LC4_C9
# !a7 & !_LC2_C3 & !_LC4_C9
# !b7 & !_LC2_C3 & !_LC4_C9
# !a7 & !b7 & !_LC2_C3;
-- Node name is ':472'
-- Equation name is '_LC7_C9', type is buried
_LC7_C9 = LCELL( _EQ014);
_EQ014 = _LC1_C2 & _LC5_C9
# _LC2_C2 & _LC5_C9;
-- Node name is ':522'
-- Equation name is '_LC2_C9', type is buried
_LC2_C9 = LCELL( _EQ015);
_EQ015 = _LC1_C2 & !_LC5_C9 & _LC8_C9
# _LC2_C2 & !_LC5_C9 & _LC8_C9
# !_LC1_C2 & !_LC2_C2 & _LC5_C9;
-- Node name is ':529'
-- Equation name is '_LC3_C9', type is buried
_LC3_C9 = LCELL( _EQ016);
_EQ016 = !_LC1_C2 & !_LC2_C2 & _LC8_C9
# _LC1_C2 & !_LC5_C9 & !_LC8_C9
# _LC1_C2 & _LC2_C2;
-- Node name is ':538'
-- Equation name is '_LC1_C9', type is buried
_LC1_C9 = LCELL( _EQ017);
_EQ017 = _LC2_C2 & !_LC5_C9 & !_LC8_C9
# !_LC1_C2 & !_LC2_C2 & _LC8_C9
# !_LC2_C2 & !_LC5_C9 & _LC8_C9
# _LC1_C2 & !_LC2_C2 & _LC5_C9;
-- Node name is ':588'
-- Equation name is '_LC6_C9', type is buried
_LC6_C9 = LCELL( _EQ018);
_EQ018 = a7 & _LC4_C9
# b7 & _LC4_C9
# a7 & b7
# _LC7_C9;
-- Node name is ':635'
-- Equation name is '_LC4_C5', type is buried
_LC4_C5 = LCELL( _EQ019);
_EQ019 = a1 & !b1 & !_LC2_B8
# !a1 & b1 & !_LC2_B8
# a1 & b1 & _LC2_B8
# !a1 & !b1 & _LC2_B8;
-- Node name is ':662'
-- Equation name is '_LC3_C5', type is buried
_LC3_C5 = LCELL( _EQ020);
_EQ020 = a1 & _LC2_B8
# a1 & b1
# b1 & _LC2_B8;
-- Node name is ':696'
-- Equation name is '_LC6_C5', type is buried
_LC6_C5 = LCELL( _EQ021);
_EQ021 = a2 & !b2 & !_LC3_C5
# !a2 & b2 & !_LC3_C5
# a2 & b2 & _LC3_C5
# !a2 & !b2 & _LC3_C5;
-- Node name is ':742'
-- Equation name is '_LC2_C5', type is buried
_LC2_C5 = LCELL( _EQ022);
_EQ022 = a2 & _LC3_C5
# a2 & b2
# b2 & _LC3_C5;
-- Node name is ':822'
-- Equation name is '_LC2_C12', type is buried
_LC2_C12 = LCELL( _EQ023);
_EQ023 = a3 & _LC2_C5
# b3 & _LC2_C5
# a3 & b3;
-- Node name is ':856'
-- Equation name is '_LC6_C2', type is buried
_LC6_C2 = LCELL( _EQ024);
_EQ024 = a4 & b4 & _LC2_C12
# !a4 & !b4 & _LC2_C12
# a4 & !b4 & !_LC2_C12
# !a4 & b4 & !_LC2_C12;
-- Node name is ':902'
-- Equation name is '_LC5_C2', type is buried
_LC5_C2 = LCELL( _EQ025);
_EQ025 = a4 & _LC2_C12
# b4 & _LC2_C12
# a4 & b4;
-- Node name is ':936'
-- Equation name is '_LC8_C2', type is buried
_LC8_C2 = LCELL( _EQ026);
_EQ026 = a5 & b5 & _LC5_C2
# !a5 & !b5 & _LC5_C2
# a5 & !b5 & !_LC5_C2
# !a5 & b5 & !_LC5_C2;
-- Node name is ':982'
-- Equation name is '_LC1_C3', type is buried
_LC1_C3 = LCELL( _EQ027);
_EQ027 = a5 & _LC5_C2
# b5 & _LC5_C2
# a5 & b5;
-- Node name is ':1016'
-- Equation name is '_LC3_C3', type is buried
_LC3_C3 = LCELL( _EQ028);
_EQ028 = a6 & b6 & _LC1_C3
# !a6 & !b6 & _LC1_C3
# a6 & !b6 & !_LC1_C3
# !a6 & b6 & !_LC1_C3;
-- Node name is ':1062'
-- Equation name is '_LC4_C9', type is buried
_LC4_C9 = LCELL( _EQ029);
_EQ029 = a6 & _LC1_C3
# b6 & _LC1_C3
# a6 & b6;
-- Node name is ':1174'
-- Equation name is '_LC8_B8', type is buried
_LC8_B8 = LCELL( _EQ030);
_EQ030 = !a0 & !b0 & cin
# a0 & !b0 & !cin
# a0 & b0 & cin
# !a0 & b0 & !cin;
-- Node name is ':1216'
-- Equation name is '_LC2_B8', type is buried
_LC2_B8 = LCELL( _EQ031);
_EQ031 = a0 & b0
# b0 & cin
# a0 & cin;
Project Information f:\byron1\neweecadd_8\eecadd_8.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:02
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:01
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:06
Memory Allocated
-----------------
Peak memory allocated during compilation = 13,526K
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