📄 eecadd_8.rpt
字号:
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
25 - - B -- OUTPUT 0 1 0 0 bcdout0
5 - - - 05 OUTPUT 0 1 0 0 bcdout1
29 - - C -- OUTPUT 0 1 0 0 bcdout2
39 - - - 11 OUTPUT 0 1 0 0 bcdout3
30 - - C -- OUTPUT 0 1 0 0 bcdout4
27 - - C -- OUTPUT 0 1 0 0 bcdout5
28 - - C -- OUTPUT 0 1 0 0 bcdout6
37 - - - 09 OUTPUT 0 1 0 0 bcdout7
38 - - - 10 OUTPUT 0 1 0 0 cout
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: f:\byron1\neweecadd_8\eecadd_8.rpt
eecadd_8
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 3 - C 02 AND2 0 4 0 1 |LPM_ADD_SUB:416|addcore:adder|:59
- 7 - C 02 OR2 2 2 1 0 |LPM_ADD_SUB:416|addcore:adder|:65
- 2 - C 02 OR2 0 3 0 4 |LPM_ADD_SUB:416|addcore:adder|:67
- 1 - C 02 OR2 0 4 0 4 |LPM_ADD_SUB:416|addcore:adder|:68
- 5 - C 09 OR2 2 2 0 4 |LPM_ADD_SUB:416|addcore:adder|:69
- 1 - C 12 OR2 2 2 0 6 :309
- 1 - C 05 OR2 0 2 0 2 :312
- 4 - C 12 OR2 2 2 1 0 :359
- 5 - C 05 OR2 0 4 1 0 :366
- 8 - C 05 OR2 0 3 1 0 :375
- 4 - C 02 OR2 s ! 2 2 0 1 ~421~1
- 2 - C 03 OR2 s ! 2 2 0 1 ~421~2
- 8 - C 09 OR2 ! 2 2 0 3 :455
- 7 - C 09 OR2 0 3 0 1 :472
- 2 - C 09 OR2 0 4 1 0 :522
- 3 - C 09 OR2 0 4 1 0 :529
- 1 - C 09 OR2 0 4 1 0 :538
- 6 - C 09 OR2 2 2 1 0 :588
- 4 - C 05 OR2 2 1 0 3 :635
- 3 - C 05 OR2 2 1 0 2 :662
- 6 - C 05 OR2 2 1 0 2 :696
- 2 - C 05 OR2 2 1 0 3 :742
- 2 - C 12 OR2 2 1 0 6 :822
- 6 - C 02 OR2 2 1 0 3 :856
- 5 - C 02 OR2 2 1 0 2 :902
- 8 - C 02 OR2 2 1 0 4 :936
- 1 - C 03 OR2 2 1 0 3 :982
- 3 - C 03 OR2 2 1 0 2 :1016
- 4 - C 09 OR2 2 1 0 3 :1062
- 8 - B 08 OR2 3 0 1 0 :1174
- 2 - B 08 OR2 3 0 0 2 :1216
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: f:\byron1\neweecadd_8\eecadd_8.rpt
eecadd_8
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 3/ 96( 3%) 1/ 48( 2%) 0/ 48( 0%) 3/16( 18%) 1/16( 6%) 0/16( 0%)
C: 10/ 96( 10%) 15/ 48( 31%) 0/ 48( 0%) 5/16( 31%) 4/16( 25%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
10: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
11: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
12: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\byron1\neweecadd_8\eecadd_8.rpt
eecadd_8
** EQUATIONS **
a0 : INPUT;
a1 : INPUT;
a2 : INPUT;
a3 : INPUT;
a4 : INPUT;
a5 : INPUT;
a6 : INPUT;
a7 : INPUT;
b0 : INPUT;
b1 : INPUT;
b2 : INPUT;
b3 : INPUT;
b4 : INPUT;
b5 : INPUT;
b6 : INPUT;
b7 : INPUT;
cin : INPUT;
-- Node name is 'bcdout0'
-- Equation name is 'bcdout0', type is output
bcdout0 = _LC8_B8;
-- Node name is 'bcdout1'
-- Equation name is 'bcdout1', type is output
bcdout1 = _LC8_C5;
-- Node name is 'bcdout2'
-- Equation name is 'bcdout2', type is output
bcdout2 = _LC5_C5;
-- Node name is 'bcdout3'
-- Equation name is 'bcdout3', type is output
bcdout3 = _LC4_C12;
-- Node name is 'bcdout4'
-- Equation name is 'bcdout4', type is output
bcdout4 = _LC7_C2;
-- Node name is 'bcdout5'
-- Equation name is 'bcdout5', type is output
bcdout5 = _LC1_C9;
-- Node name is 'bcdout6'
-- Equation name is 'bcdout6', type is output
bcdout6 = _LC3_C9;
-- Node name is 'bcdout7'
-- Equation name is 'bcdout7', type is output
bcdout7 = _LC2_C9;
-- Node name is 'cout'
-- Equation name is 'cout', type is output
cout = _LC6_C9;
-- Node name is '|LPM_ADD_SUB:416|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_C2', type is buried
_LC3_C2 = LCELL( _EQ001);
_EQ001 = _LC1_C12 & _LC3_C3 & _LC6_C2 & _LC8_C2;
-- Node name is '|LPM_ADD_SUB:416|addcore:adder|:65' from file "addcore.tdf" line 315, column 26
-- Equation name is '_LC7_C2', type is buried
_LC7_C2 = LCELL( _EQ002);
_EQ002 = a4 & !b4 & !_LC1_C12 & !_LC2_C12
# !a4 & b4 & !_LC1_C12 & !_LC2_C12
# a4 & b4 & !_LC1_C12 & _LC2_C12
# !a4 & !b4 & !_LC1_C12 & _LC2_C12
# a4 & !b4 & _LC1_C12 & _LC2_C12
# !a4 & b4 & _LC1_C12 & _LC2_C12
# a4 & b4 & _LC1_C12 & !_LC2_C12
# !a4 & !b4 & _LC1_C12 & !_LC2_C12;
-- Node name is '|LPM_ADD_SUB:416|addcore:adder|:67' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC2_C2', type is buried
_LC2_C2 = LCELL( _EQ003);
_EQ003 = !_LC6_C2 & _LC8_C2
# !_LC1_C12 & _LC8_C2
# _LC1_C12 & _LC6_C2 & !_LC8_C2;
-- Node name is '|LPM_ADD_SUB:416|addcore:adder|:68' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC1_C2', type is buried
_LC1_C2 = LCELL( _EQ004);
_EQ004 = _LC3_C3 & !_LC6_C2
# !_LC1_C12 & _LC3_C3
# _LC3_C3 & !_LC8_C2
# _LC1_C12 & !_LC3_C3 & _LC6_C2 & _LC8_C2;
-- Node name is '|LPM_ADD_SUB:416|addcore:adder|:69' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC5_C9', type is buried
_LC5_C9 = LCELL( _EQ005);
_EQ005 = a7 & b7 & !_LC3_C2 & _LC4_C9
# !a7 & !b7 & !_LC3_C2 & _LC4_C9
# a7 & !b7 & !_LC3_C2 & !_LC4_C9
# !a7 & b7 & !_LC3_C2 & !_LC4_C9
# a7 & !b7 & _LC3_C2 & _LC4_C9
# !a7 & b7 & _LC3_C2 & _LC4_C9
# a7 & b7 & _LC3_C2 & !_LC4_C9
# !a7 & !b7 & _LC3_C2 & !_LC4_C9;
-- Node name is ':309'
-- Equation name is '_LC1_C12', type is buried
_LC1_C12 = LCELL( _EQ006);
_EQ006 = a3 & b3 & _LC1_C5 & _LC2_C5
# !a3 & !b3 & _LC1_C5 & _LC2_C5
# a3 & !b3 & _LC1_C5 & !_LC2_C5
# !a3 & b3 & _LC1_C5 & !_LC2_C5;
-- Node name is ':312'
-- Equation name is '_LC1_C5', type is buried
_LC1_C5 = LCELL( _EQ007);
_EQ007 = _LC4_C5
# _LC6_C5;
-- Node name is ':359'
-- Equation name is '_LC4_C12', type is buried
_LC4_C12 = LCELL( _EQ008);
_EQ008 = a3 & b3 & !_LC1_C5 & _LC2_C5
# a3 & !b3 & _LC1_C5 & _LC2_C5
# !a3 & b3 & _LC1_C5 & _LC2_C5
# a3 & b3 & _LC1_C5 & !_LC2_C5
# a3 & !b3 & !_LC1_C5 & !_LC2_C5
# !a3 & b3 & !_LC1_C5 & !_LC2_C5
# !a3 & !b3 & !_LC1_C5 & _LC2_C5;
-- Node name is ':366'
-- Equation name is '_LC5_C5', type is buried
_LC5_C5 = LCELL( _EQ009);
_EQ009 = _LC1_C12 & _LC4_C5 & _LC6_C5
# _LC1_C12 & !_LC4_C5 & !_LC6_C5
# _LC2_C12 & _LC4_C5 & _LC6_C5
# _LC2_C12 & !_LC4_C5 & !_LC6_C5
# !_LC1_C12 & !_LC2_C12 & _LC6_C5;
-- Node name is ':375'
-- Equation name is '_LC8_C5', type is buried
_LC8_C5 = LCELL( _EQ010);
_EQ010 = _LC1_C12 & !_LC4_C5
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