eecadd_8.fit.summary

来自「此程序用VHDL语言编写」· SUMMARY 代码 · 共 13 行

Fitter Status : Successful - Wed Apr 30 16:51:30 2008
Quartus II Version : 5.1 Build 176 10/26/2005 SJ Full Version
Revision Name : eecadd_8
Top-level Entity Name : eecadd_8
Family : APEX20KE
Device : EP20K300EQC240-1
Timing Models : Final
Total logic elements : 39 / 11,520 ( < 1 % )
Total pins : 26 / 152 ( 17 % )
Total virtual pins : 0
Total memory bits : 0 / 147,456 ( 0 % )
Total PLLs : 0