eecadd_8.map.rpt

此程序用VHDL语言编写

; Auto Shift Register Replacement                                                            ; On               ; On            ;
; Auto Clock Enable Replacement                                                              ; On               ; On            ;
; Auto Resource Sharing                                                                      ; Off              ; Off           ;
; Allow Any RAM Size For Recognition                                                         ; Off              ; Off           ;
; Allow Any ROM Size For Recognition                                                         ; Off              ; Off           ;
; Allow Any Shift Register Size For Recognition                                              ; Off              ; Off           ;
; Ignore translate_off and translate_on Synthesis Directives                                 ; Off              ; Off           ;
; Show Parameter Settings Tables in Synthesis Report                                         ; On               ; On            ;
; Ignore Maximum Fan-Out Assignments                                                         ; Off              ; Off           ;
; Retiming Meta-Stability Register Sequence Length                                           ; 2                ; 2             ;
; HDL message level                                                                          ; Level2           ; Level2        ;
+--------------------------------------------------------------------------------------------+------------------+---------------+


+-----------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                    ;
+----------------------------------+-----------------+-----------------+------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type       ; File Name with Absolute Path       ;
+----------------------------------+-----------------+-----------------+------------------------------------+
; eecadd_8.vhd                     ; yes             ; User VHDL File  ; F:/byron1/neweecadd_8/eecadd_8.vhd ;
+----------------------------------+-----------------+-----------------+------------------------------------+


+-----------------------------------------------+
; Analysis & Synthesis Resource Usage Summary   ;
+-----------------------------------+-----------+
; Resource                          ; Usage     ;
+-----------------------------------+-----------+
; Total logic elements              ; 39        ;
; Total combinational functions     ; 39        ;
;     -- Total 4-input functions    ; 13        ;
;     -- Total 3-input functions    ; 18        ;
;     -- Total 2-input functions    ; 5         ;
;     -- Total 1-input functions    ; 3         ;
;     -- Total 0-input functions    ; 0         ;
; Combinational cells for routing   ; 0         ;
; Total registers                   ; 0         ;
; Total logic cells in carry chains ; 4         ;
; I/O pins                          ; 26        ;
; Maximum fan-out node              ; co[3]~320 ;
; Maximum fan-out                   ; 7         ;
; Total fan-out                     ; 131       ;
; Average fan-out                   ; 2.02      ;
+-----------------------------------+-----------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                    ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; |eecadd_8                  ; 39 (39)     ; 0            ; 0           ; 26   ; 0            ; 39 (39)      ; 0 (0)             ; 0 (0)            ; 4 (4)           ; 0 (0)      ; |eecadd_8           ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 0     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in F:/byron1/neweecadd_8/eecadd_8.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Wed Apr 30 16:51:16 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off eecadd_8 -c eecadd_8
Info: Found 2 design units, including 1 entities, in source file eecadd_8.vhd
    Info: Found design unit 1: eecadd_8-arch
    Info: Found entity 1: eecadd_8
Info: Elaborating entity "eecadd_8" for the top level hierarchy
Info: Implemented 65 device resources after synthesis - the final resource count might be different
    Info: Implemented 17 input pins
    Info: Implemented 9 output pins
    Info: Implemented 39 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
    Info: Processing ended: Wed Apr 30 16:51:18 2008
    Info: Elapsed time: 00:00:03