eecadd_8.map.summary

此程序用VHDL语言编写

Analysis & Synthesis Status : Successful - Wed Apr 30 16:51:18 2008
Quartus II Version : 5.1 Build 176 10/26/2005 SJ Full Version
Revision Name : eecadd_8
Top-level Entity Name : eecadd_8
Family : APEX20KE
Total logic elements : 39
Total pins : 26
Total virtual pins : 0
Total memory bits : 0
Total PLLs : 0