eecadd_8.vhd

此程序用VHDL语言编写

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity eecadd_8 is
port( a: in std_logic_vector(7 downto 0);
    b: in std_logic_vector(7 downto 0);
    cin:in std_logic;
    bcdout: out std_logic_vector(7 downto 0);
    cout:out std_logic );
end eecadd_8;
architecture arch of eecadd_8 is
  signal co:std_logic_vector(7 downto 0);
  signal y:std_logic_vector(7 downto 0);
  begin
     y(0)<=a(0)xor b(0)xor cin;
     co(0)<=(a(0)and b(0))or(b(0)and cin)or(a(0)and cin);
       gen:for I in 1 to 7 generate
          y(I)<=a(I)xor b(I)xor co(I-1);
          co(I)<=(co(I-1)and a(I)) or (co(I-1)and b(I))or (a(I)and b(I));
     end generate;
 process(a,b,y,co(7))
    procedure bcd_change(data_in:inout std_logic_vector(3 downto 0);
                         data_cin:in std_logic;
                         data_out:out std_logic_vector(3 downto 0);
                         data_cout:out std_logic)is
    begin
      if(data_in>"1001")then
      data_out:=data_in+"0110";
      data_cout:='1';
      elsif(data_cin='1')then
      data_out:=data_in+"0110";
      data_cout:='0';
      else
      data_out:=data_in;
      data_cout:='0';
      end if;
    end bcd_change;
    variable d,e,coo:std_logic_vector(7 downto 0);
    variable f,g:std_logic_vector(3 downto 0);
    variable s:std_logic_vector(2 downto 0);
	begin
     d:=y;
     coo:=co;
     bcd_change(d(3 downto 0),coo(3),e(3 downto 0),s(0));
     f:="000"&s(0);
     g:=d(7 downto 4)+f;
     if(d(7 downto 4)="1111")then
     s(1):='1';
     else
     s(1):=coo(7);
     end if;
    bcd_change(g,s(1),e(7 downto 4),s(2));
    bcdout<=e;
    cout<=s(2) or co(7);          
end process;
end arch;