zmd_1.vhd

用VHDL描述一个由8个发光二极管组成的走马灯。有系统复位。单点移动模式：一个点在8个发光二极管上来回的亮。幕布式：从中间两个点

library IEEE;                           --底层文件
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity zmd_2 is
  port(
     clk:in std_logic;
     reset:in std_logic;
     clkout1:out std_logic_vector(7 downto 0)
    );
end zmd_2;
architecture zmd_2_arch of zmd_2 is
type state is (s0,s1,s2,s3,s4,s5,s6,s7,s8,s9,s10,s11,s12,s13,s14);
signal a1,next_state1:state;
begin
p1:process(a1,reset)
 begin
       case a1 is
        when s0=>if(reset='0')then next_state1<=s1; --第1个亮
          else next_state1<=s0; end if;
        when s1=>if(reset='0')then next_state1<=s2; --第2个亮
          else next_state1<=s0; end if;
        when s2=>if(reset='0')then next_state1<=s3; --第3个亮
          else next_state1<=s0; end if;
        when s3=>if(reset='0')then next_state1<=s4; --第4个亮
          else next_state1<=s0; end if;
        when s4=>if(reset='0')then next_state1<=s5; --第5个亮
          else next_state1<=s0; end if;
        when s5=>if(reset='0')then next_state1<=s6; --第6个亮
          else next_state1<=s0; end if;
        when s6=>if(reset='0')then next_state1<=s7; --第7个亮
          else next_state1<=s0; end if;
        when s7=>if(reset='0')then next_state1<=s8; --第8个亮
          else next_state1<=s0; end if;
        when s8=>if(reset='0')then next_state1<=s9; --第7个亮
          else next_state1<=s0; end if;
        when s9=>if(reset='0')then next_state1<=s10; --第6个亮
          else next_state1<=s0; end if;
        when s10=>if(reset='0')then next_state1<=s11; --第5个亮
          else next_state1<=s0; end if;
        when s11=>if(reset='0')then next_state1<=s12; --第4个亮
          else next_state1<=s0; end if;
        when s12=>if(reset='0')then next_state1<=s13; --第3个亮
          else next_state1<=s0; end if;
        when s13=>if(reset='0')then next_state1<=s14; --第2个亮
          else next_state1<=s0; end if;
        when s14=>if(reset='0')then next_state1<=s1; --第1个亮
          else next_state1<=s0; end if;
end case;
end process;
p2:process(clk)
begin
if(clk'event and clk='1')then
a1<=next_state1;
end if;
end process;
p3:process(a1)
 begin
       case a1 is
        when s0=> clkout1<="00000000"; -- 全灭
        when s1=> clkout1<="10000000"; --第1个亮
        when s2=> clkout1<="01000000"; --  2
        when s3=> clkout1<="00100000"; --  3
        when s4=> clkout1<="00010000"; --  4
        when s5=> clkout1<="00001000"; --  5
        when s6=> clkout1<="00000100"; --  6
        when s7=> clkout1<="00000010"; --  7
        when s8=> clkout1<="00000001"; --  8
        when s9=> clkout1<="00000010"; --  7
        when s10=> clkout1<="00000100"; -- 6
        when s11=> clkout1<="00001000"; -- 5
        when s12=> clkout1<="00010000"; -- 4
        when s13=> clkout1<="00100000"; -- 3
        when s14=> clkout1<="01000000"; -- 2
       end case;
end process;
end;


library IEEE;                           --底层文件
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity zmd_3 is
  port(
     clk:in std_logic;
     reset:in std_logic;
     clkout2:out std_logic_vector(7 downto 0)
    );
end zmd_3;
architecture zmd_3_arch of zmd_3 is
type state is (g0,g1,g2,g3,g4,g5,g6,g7);
signal a2,next_state2:state;
begin
p1:process(a2,reset)
 begin
       case a2 is
        when g0=>if(reset='0')then next_state2<=g1; --中间2个亮
          else next_state2<=g0; end if;
        when g1=>if(reset='0')then next_state2<=g2; --中间4个亮
          else next_state2<=g0; end if;
        when g2=>if(reset='0')then next_state2<=g3; --中间6个亮
          else next_state2<=g0; end if;
        when g3=>if(reset='0')then next_state2<=g4; --中间8个亮
          else next_state2<=g0; end if;
        when g4=>if(reset='0')then next_state2<=g5; --中间6个亮
          else next_state2<=g0; end if;
        when g5=>if(reset='0')then next_state2<=g6; --中间4个亮
          else next_state2<=g0; end if;
        when g6=>if(reset='0')then next_state2<=g7; --中间2个亮
          else next_state2<=g0; end if;
        when g7=>if(reset='0')then next_state2<=g0; --全灭
          else next_state2<=g0; end if;
end case;
end process;
p2:process(clk)
begin
if(clk'event and clk='1')then
a2<=next_state2;
end if;
end process;
p3:process(a2)
 begin
       case a2 is
        when g0=> clkout2<="00000000"; --全灭
        when g1=> clkout2<="00011000"; --中间2个亮
        when g2=> clkout2<="00111100"; --中间4个亮
        when g3=> clkout2<="01111110"; --中间6个亮
        when g4=> clkout2<="11111111"; --中间8个亮,全亮
        when g5=> clkout2<="01111110"; --中间6个亮
        when g6=> clkout2<="00111100"; --中间4个亮
        when g7=> clkout2<="00011000"; --中间2个亮
       end case;
end process;
end;

library IEEE;                           --顶层文件
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity zmd_1 is
  port(
     clk:in std_logic;
     reset:in std_logic;
     trans:in std_logic;
     clkout:out std_logic_vector(7 downto 0)
    );
end zmd_1;
architecture zmd_1_arch of zmd_1 is   
component zmd_2                       
  port(
     clk:in std_logic;
     reset:in std_logic;
     clkout1:out std_logic_vector(7 downto 0)
    );
end component;
component  zmd_3
  port(
     clk:in std_logic;
     reset:in std_logic;
     clkout2:out std_logic_vector(7 downto 0)
    );
end component;
type temp is(temp0,temp1,temp2);
signal t:temp;
signal c1,c2:std_logic_vector(7 downto 0);
begin
process(trans)
begin
if(trans'event and trans='1') then
    case t is
       when temp0=> t <=temp1;
       when temp1=> t <=temp2; 
       when temp2=> t <=temp1; 
    end case; 
  end if;
end process;
process(t)
 begin
   case t is
      when temp0=> clkout <="00000000";
      when temp1=> clkout <=c1;
      when temp2=> clkout <=c2;
   end case;
end process; 
u1:zmd_2 port map(clk=>clk,reset=>reset,clkout1=>c1);
u2:zmd_3 port map(clk=>clk,reset=>reset,clkout2=>c2);
end;