dptrafficlight.tan.qmsg

用VHDL实现交通灯的功能 很实用的 我认为比其他的的交通灯程序更好

{ "Info" "ITDB_TSU_RESULT" "KeyDebounce:inst5\|inst Reset Clock 2.181 ns register " "Info: tsu for register \"KeyDebounce:inst5\|inst\" (data pin = \"Reset\", clock pin = \"Clock\") is 2.181 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.862 ns + Longest pin register " "Info: + Longest pin to register delay is 9.862 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns Reset 1 PIN PIN_158 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_158; Fanout = 1; PIN Node = 'Reset'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { Reset } "NODE_NAME" } } { "DPTrafficLight.bdf" "" { Schematic "F:/DPA_4_TrafficLight/DPTrafficLight.bdf" { { 144 88 256 160 "Reset" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(8.278 ns) + CELL(0.115 ns) 9.862 ns KeyDebounce:inst5\|inst 2 REG LC_X24_Y13_N5 2 " "Info: 2: + IC(8.278 ns) + CELL(0.115 ns) = 9.862 ns; Loc. = LC_X24_Y13_N5; Fanout = 2; REG Node = 'KeyDebounce:inst5\|inst'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.393 ns" { Reset KeyDebounce:inst5|inst } "NODE_NAME" } } { "KeyDebounce.bdf" "" { Schematic "F:/DPA_4_TrafficLight/KeyDebounce.bdf" { { 264 240 304 344 "inst" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.584 ns ( 16.06 % ) " "Info: Total cell delay = 1.584 ns ( 16.06 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.278 ns ( 83.94 % ) " "Info: Total interconnect delay = 8.278 ns ( 83.94 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "9.862 ns" { Reset KeyDebounce:inst5|inst } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "9.862 ns" { Reset Reset~out0 KeyDebounce:inst5|inst } { 0.000ns 0.000ns 8.278ns } { 0.000ns 1.469ns 0.115ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "KeyDebounce.bdf" "" { Schematic "F:/DPA_4_TrafficLight/KeyDebounce.bdf" { { 264 240 304 344 "inst" "" } } } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clock destination 7.718 ns - Shortest register " "Info: - Shortest clock path from clock \"Clock\" to destination register is 7.718 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns Clock 1 CLK PIN_28 66 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 66; CLK Node = 'Clock'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { Clock } "NODE_NAME" } } { "DPTrafficLight.bdf" "" { Schematic "F:/DPA_4_TrafficLight/DPTrafficLight.bdf" { { 392 -88 80 408 "Clock" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.998 ns) + CELL(0.935 ns) 3.402 ns int_div:inst\|clock_out_r 2 REG LC_X45_Y13_N2 10 " "Info: 2: + IC(0.998 ns) + CELL(0.935 ns) = 3.402 ns; Loc. = LC_X45_Y13_N2; Fanout = 10; REG Node = 'int_div:inst\|clock_out_r'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.933 ns" { Clock int_div:inst|clock_out_r } "NODE_NAME" } } { "int_div.vhd" "" { Text "F:/DPA_4_TrafficLight/int_div.vhd" 87 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.605 ns) + CELL(0.711 ns) 7.718 ns KeyDebounce:inst5\|inst 3 REG LC_X24_Y13_N5 2 " "Info: 3: + IC(3.605 ns) + CELL(0.711 ns) = 7.718 ns; Loc. = LC_X24_Y13_N5; Fanout = 2; REG Node = 'KeyDebounce:inst5\|inst'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.316 ns" { int_div:inst|clock_out_r KeyDebounce:inst5|inst } "NODE_NAME" } } { "KeyDebounce.bdf" "" { Schematic "F:/DPA_4_TrafficLight/KeyDebounce.bdf" { { 264 240 304 344 "inst" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 40.36 % ) " "Info: Total cell delay = 3.115 ns ( 40.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.603 ns ( 59.64 % ) " "Info: Total interconnect delay = 4.603 ns ( 59.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.718 ns" { Clock int_div:inst|clock_out_r KeyDebounce:inst5|inst } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.718 ns" { Clock Clock~out0 int_div:inst|clock_out_r KeyDebounce:inst5|inst } { 0.000ns 0.000ns 0.998ns 3.605ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "9.862 ns" { Reset KeyDebounce:inst5|inst } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "9.862 ns" { Reset Reset~out0 KeyDebounce:inst5|inst } { 0.000ns 0.000ns 8.278ns } { 0.000ns 1.469ns 0.115ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.718 ns" { Clock int_div:inst|clock_out_r KeyDebounce:inst5|inst } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.718 ns" { Clock Clock~out0 int_div:inst|clock_out_r KeyDebounce:inst5|inst } { 0.000ns 0.000ns 0.998ns 3.605ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "Clock SEG\[0\] TrafficLight:inst6\|Count0\[0\] 18.509 ns register " "Info: tco from clock \"Clock\" to destination pin \"SEG\[0\]\" through register \"TrafficLight:inst6\|Count0\[0\]\" is 18.509 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clock source 7.721 ns + Longest register " "Info: + Longest clock path from clock \"Clock\" to source register is 7.721 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns Clock 1 CLK PIN_28 66 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 66; CLK Node = 'Clock'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { Clock } "NODE_NAME" } } { "DPTrafficLight.bdf" "" { Schematic "F:/DPA_4_TrafficLight/DPTrafficLight.bdf" { { 392 -88 80 408 "Clock" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.031 ns) + CELL(0.935 ns) 3.435 ns int_div:inst14\|clock_out_r 2 REG LC_X8_Y13_N2 13 " "Info: 2: + IC(1.031 ns) + CELL(0.935 ns) = 3.435 ns; Loc. = LC_X8_Y13_N2; Fanout = 13; REG Node = 'int_div:inst14\|clock_out_r'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.966 ns" { Clock int_div:inst14|clock_out_r } "NODE_NAME" } } { "int_div.vhd" "" { Text "F:/DPA_4_TrafficLight/int_div.vhd" 87 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.575 ns) + CELL(0.711 ns) 7.721 ns TrafficLight:inst6\|Count0\[0\] 3 REG LC_X25_Y11_N1 8 " "Info: 3: + IC(3.575 ns) + CELL(0.711 ns) = 7.721 ns; Loc. = LC_X25_Y11_N1; Fanout = 8; REG Node = 'TrafficLight:inst6\|Count0\[0\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.286 ns" { int_div:inst14|clock_out_r TrafficLight:inst6|Count0[0] } "NODE_NAME" } } { "Trafficlight.vhd" "" { Text "F:/DPA_4_TrafficLight/Trafficlight.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 40.34 % ) " "Info: Total cell delay = 3.115 ns ( 40.34 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.606 ns ( 59.66 % ) " "Info: Total interconnect delay = 4.606 ns ( 59.66 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.721 ns" { Clock int_div:inst14|clock_out_r TrafficLight:inst6|Count0[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.721 ns" { Clock Clock~out0 int_div:inst14|clock_out_r TrafficLight:inst6|Count0[0] } { 0.000ns 0.000ns 1.031ns 3.575ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "Trafficlight.vhd" "" { Text "F:/DPA_4_TrafficLight/Trafficlight.vhd" 30 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.564 ns + Longest register pin " "Info: + Longest register to pin delay is 10.564 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns TrafficLight:inst6\|Count0\[0\] 1 REG LC_X25_Y11_N1 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X25_Y11_N1; Fanout = 8; REG Node = 'TrafficLight:inst6\|Count0\[0\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { TrafficLight:inst6|Count0[0] } "NODE_NAME" } } { "Trafficlight.vhd" "" { Text "F:/DPA_4_TrafficLight/Trafficlight.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.821 ns) + CELL(0.114 ns) 2.935 ns BCDOutput:inst4\|scanled:inst1\|seg\[0\]~40 2 COMB LC_X36_Y14_N1 7 " "Info: 2: + IC(2.821 ns) + CELL(0.114 ns) = 2.935 ns; Loc. = LC_X36_Y14_N1; Fanout = 7; COMB Node = 'BCDOutput:inst4\|scanled:inst1\|seg\[0\]~40'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.935 ns" { TrafficLight:inst6|Count0[0] BCDOutput:inst4|scanled:inst1|seg[0]~40 } "NODE_NAME" } } { "ScanLED.vhd" "" { Text "F:/DPA_4_TrafficLight/ScanLED.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.565 ns) + CELL(0.292 ns) 4.792 ns BCDOutput:inst4\|decl7s:inst\|WideOr6~15 3 COMB LC_X38_Y13_N2 1 " "Info: 3: + IC(1.565 ns) + CELL(0.292 ns) = 4.792 ns; Loc. = LC_X38_Y13_N2; Fanout = 1; COMB Node = 'BCDOutput:inst4\|decl7s:inst\|WideOr6~15'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.857 ns" { BCDOutput:inst4|scanled:inst1|seg[0]~40 BCDOutput:inst4|decl7s:inst|WideOr6~15 } "NODE_NAME" } } { "decl7s.v" "" { Text "F:/DPA_4_TrafficLight/decl7s.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.648 ns) + CELL(2.124 ns) 10.564 ns SEG\[0\] 4 PIN PIN_169 0 " "Info: 4: + IC(3.648 ns) + CELL(2.124 ns) = 10.564 ns; Loc. = PIN_169; Fanout = 0; PIN Node = 'SEG\[0\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.772 ns" { BCDOutput:inst4|decl7s:inst|WideOr6~15 SEG[0] } "NODE_NAME" } } { "DPTrafficLight.bdf" "" { Schematic "F:/DPA_4_TrafficLight/DPTrafficLight.bdf" { { 392 992 1168 408 "SEG\[7..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.530 ns ( 23.95 % ) " "Info: Total cell delay = 2.530 ns ( 23.95 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.034 ns ( 76.05 % ) " "Info: Total interconnect delay = 8.034 ns ( 76.05 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "10.564 ns" { TrafficLight:inst6|Count0[0] BCDOutput:inst4|scanled:inst1|seg[0]~40 BCDOutput:inst4|decl7s:inst|WideOr6~15 SEG[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "10.564 ns" { TrafficLight:inst6|Count0[0] BCDOutput:inst4|scanled:inst1|seg[0]~40 BCDOutput:inst4|decl7s:inst|WideOr6~15 SEG[0] } { 0.000ns 2.821ns 1.565ns 3.648ns } { 0.000ns 0.114ns 0.292ns 2.124ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.721 ns" { Clock int_div:inst14|clock_out_r TrafficLight:inst6|Count0[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.721 ns" { Clock Clock~out0 int_div:inst14|clock_out_r TrafficLight:inst6|Count0[0] } { 0.000ns 0.000ns 1.031ns 3.575ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "10.564 ns" { TrafficLight:inst6|Count0[0] BCDOutput:inst4|scanled:inst1|seg[0]~40 BCDOutput:inst4|decl7s:inst|WideOr6~15 SEG[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "10.564 ns" { TrafficLight:inst6|Count0[0] BCDOutput:inst4|scanled:inst1|seg[0]~40 BCDOutput:inst4|decl7s:inst|WideOr6~15 SEG[0] } { 0.000ns 2.821ns 1.565ns 3.648ns } { 0.000ns 0.114ns 0.292ns 2.124ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "KeyDebounce:inst13\|inst Sensor Clock -2.058 ns register " "Info: th for register \"KeyDebounce:inst13\|inst\" (data pin = \"Sensor\", clock pin = \"Clock\") is -2.058 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clock destination 7.685 ns + Longest register " "Info: + Longest clock path from clock \"Clock\" to destination register is 7.685 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns Clock 1 CLK PIN_28 66 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 66; CLK Node = 'Clock'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { Clock } "NODE_NAME" } } { "DPTrafficLight.bdf" "" { Schematic "F:/DPA_4_TrafficLight/DPTrafficLight.bdf" { { 392 -88 80 408 "Clock" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.998 ns) + CELL(0.935 ns) 3.402 ns int_div:inst\|clock_out_r 2 REG LC_X45_Y13_N2 10 " "Info: 2: + IC(0.998 ns) + CELL(0.935 ns) = 3.402 ns; Loc. = LC_X45_Y13_N2; Fanout = 10; REG Node = 'int_div:inst\|clock_out_r'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.933 ns" { Clock int_div:inst|clock_out_r } "NODE_NAME" } } { "int_div.vhd" "" { Text "F:/DPA_4_TrafficLight/int_div.vhd" 87 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.572 ns) + CELL(0.711 ns) 7.685 ns KeyDebounce:inst13\|inst 3 REG LC_X24_Y11_N7 2 " "Info: 3: + IC(3.572 ns) + CELL(0.711 ns) = 7.685 ns; Loc. = LC_X24_Y11_N7; Fanout = 2; REG Node = 'KeyDebounce:inst13\|inst'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.283 ns" { int_div:inst|clock_out_r KeyDebounce:inst13|inst } "NODE_NAME" } } { "KeyDebounce.bdf" "" { Schematic "F:/DPA_4_TrafficLight/KeyDebounce.bdf" { { 264 240 304 344 "inst" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 40.53 % ) " "Info: Total cell delay = 3.115 ns ( 40.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.570 ns ( 59.47 % ) " "Info: Total interconnect delay = 4.570 ns ( 59.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.685 ns" { Clock int_div:inst|clock_out_r KeyDebounce:inst13|inst } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.685 ns" { Clock Clock~out0 int_div:inst|clock_out_r KeyDebounce:inst13|inst } { 0.000ns 0.000ns 0.998ns 3.572ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "KeyDebounce.bdf" "" { Schematic "F:/DPA_4_TrafficLight/KeyDebounce.bdf" { { 264 240 304 344 "inst" "" } } } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.758 ns - Shortest pin register " "Info: - Shortest pin to register delay is 9.758 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns Sensor 1 PIN PIN_156 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_156; Fanout = 1; PIN Node = 'Sensor'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { Sensor } "NODE_NAME" } } { "DPTrafficLight.bdf" "" { Schematic "F:/DPA_4_TrafficLight/DPTrafficLight.bdf" { { 256 88 256 272 "Sensor" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(8.174 ns) + CELL(0.115 ns) 9.758 ns KeyDebounce:inst13\|inst 2 REG LC_X24_Y11_N7 2 " "Info: 2: + IC(8.174 ns) + CELL(0.115 ns) = 9.758 ns; Loc. = LC_X24_Y11_N7; Fanout = 2; REG Node = 'KeyDebounce:inst13\|inst'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.289 ns" { Sensor KeyDebounce:inst13|inst } "NODE_NAME" } } { "KeyDebounce.bdf" "" { Schematic "F:/DPA_4_TrafficLight/KeyDebounce.bdf" { { 264 240 304 344 "inst" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.584 ns ( 16.23 % ) " "Info: Total cell delay = 1.584 ns ( 16.23 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.174 ns ( 83.77 % ) " "Info: Total interconnect delay = 8.174 ns ( 83.77 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "9.758 ns" { Sensor KeyDebounce:inst13|inst } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "9.758 ns" { Sensor Sensor~out0 KeyDebounce:inst13|inst } { 0.000ns 0.000ns 8.174ns } { 0.000ns 1.469ns 0.115ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.685 ns" { Clock int_div:inst|clock_out_r KeyDebounce:inst13|inst } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.685 ns" { Clock Clock~out0 int_div:inst|clock_out_r KeyDebounce:inst13|inst } { 0.000ns 0.000ns 0.998ns 3.572ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "9.758 ns" { Sensor KeyDebounce:inst13|inst } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "9.758 ns" { Sensor Sensor~out0 KeyDebounce:inst13|inst } { 0.000ns 0.000ns 8.174ns } { 0.000ns 1.469ns 0.115ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}