dptrafficlight.hier_info

用VHDL实现交通灯的功能 很实用的 我认为比其他的的交通灯程序更好

|DPTrafficLight
SensorLED <= inst3.DB_MAX_OUTPUT_PORT_TYPE
Sensor => KeyDebounce:inst13.KeyIn
Clock => int_div:inst.clock
Clock => int_div:inst1.clock
Clock => int_div:inst14.clock
ResetLED <= inst2.DB_MAX_OUTPUT_PORT_TYPE
Reset => KeyDebounce:inst5.KeyIn
DIG[0] <= BCDOutput:inst4.DIGOutput[0]
DIG[1] <= BCDOutput:inst4.DIGOutput[1]
Light[0] <= TrafficLight:inst6.Light[0]
Light[1] <= TrafficLight:inst6.Light[1]
Light[2] <= TrafficLight:inst6.Light[2]
Light[3] <= TrafficLight:inst6.Light[3]
Light[4] <= TrafficLight:inst6.Light[4]
Light[5] <= TrafficLight:inst6.Light[5]
SEG[0] <= BCDOutput:inst4.SEGOutput[0]
SEG[1] <= BCDOutput:inst4.SEGOutput[1]
SEG[2] <= BCDOutput:inst4.SEGOutput[2]
SEG[3] <= BCDOutput:inst4.SEGOutput[3]
SEG[4] <= BCDOutput:inst4.SEGOutput[4]
SEG[5] <= BCDOutput:inst4.SEGOutput[5]
SEG[6] <= BCDOutput:inst4.SEGOutput[6]
SEG[7] <= BCDOutput:inst4.SEGOutput[7]


|DPTrafficLight|KeyDebounce:inst13
KeyOut <= inst3.DB_MAX_OUTPUT_PORT_TYPE
Clock => inst.CLK
Clock => inst2.CLK
Clock => inst1.CLK
Clock => inst4.CLK
Clock => inst5.CLK
KeyIn => inst.DATAIN


|DPTrafficLight|int_div:inst
clock => count_p[18].CLK
clock => count_p[17].CLK
clock => count_p[16].CLK
clock => count_p[15].CLK
clock => count_p[14].CLK
clock => count_p[13].CLK
clock => count_p[12].CLK
clock => count_p[11].CLK
clock => count_p[10].CLK
clock => count_p[9].CLK
clock => count_p[8].CLK
clock => count_p[7].CLK
clock => count_p[6].CLK
clock => count_p[5].CLK
clock => count_p[4].CLK
clock => count_p[3].CLK
clock => count_p[2].CLK
clock => count_p[1].CLK
clock => count_p[0].CLK
clock => clk_p_r.CLK
clock => clock_out_r.CLK
clock_out <= clock_out_r.DB_MAX_OUTPUT_PORT_TYPE


|DPTrafficLight|KeyDebounce:inst5
KeyOut <= inst3.DB_MAX_OUTPUT_PORT_TYPE
Clock => inst.CLK
Clock => inst2.CLK
Clock => inst1.CLK
Clock => inst4.CLK
Clock => inst5.CLK
KeyIn => inst.DATAIN


|DPTrafficLight|BCDOutput:inst4
DIGOutput[0] <= scanled:inst1.dig[0]
DIGOutput[1] <= scanled:inst1.dig[1]
CLK => scanled:inst1.clk1k
BCDInput[0] => scanled:inst1.d[0]
BCDInput[1] => scanled:inst1.d[1]
BCDInput[2] => scanled:inst1.d[2]
BCDInput[3] => scanled:inst1.d[3]
BCDInput[4] => scanled:inst1.d[4]
BCDInput[5] => scanled:inst1.d[5]
BCDInput[6] => scanled:inst1.d[6]
BCDInput[7] => scanled:inst1.d[7]
SEGOutput[0] <= decl7s:inst.seg[0]
SEGOutput[1] <= decl7s:inst.seg[1]
SEGOutput[2] <= decl7s:inst.seg[2]
SEGOutput[3] <= decl7s:inst.seg[3]
SEGOutput[4] <= decl7s:inst.seg[4]
SEGOutput[5] <= decl7s:inst.seg[5]
SEGOutput[6] <= decl7s:inst.seg[6]
SEGOutput[7] <= decl7s:inst.seg[7]


|DPTrafficLight|BCDOutput:inst4|scanled:inst1
d[0] => seg~3.DATAA
d[1] => seg~2.DATAA
d[2] => seg~1.DATAA
d[3] => seg~0.DATAA
d[4] => seg~3.DATAB
d[5] => seg~2.DATAB
d[6] => seg~1.DATAB
d[7] => seg~0.DATAB
clk1k => seg~3.OUTPUTSELECT
clk1k => seg~2.OUTPUTSELECT
clk1k => seg~1.OUTPUTSELECT
clk1k => seg~0.OUTPUTSELECT
clk1k => dig[1].DATAIN
clk1k => dig[0].DATAIN
seg[0] <= seg~3.DB_MAX_OUTPUT_PORT_TYPE
seg[1] <= seg~2.DB_MAX_OUTPUT_PORT_TYPE
seg[2] <= seg~1.DB_MAX_OUTPUT_PORT_TYPE
seg[3] <= seg~0.DB_MAX_OUTPUT_PORT_TYPE
dig[0] <= clk1k.DB_MAX_OUTPUT_PORT_TYPE
dig[1] <= clk1k.DB_MAX_OUTPUT_PORT_TYPE


|DPTrafficLight|BCDOutput:inst4|decl7s:inst
d[0] => Decoder0.IN3
d[1] => Decoder0.IN2
d[2] => Decoder0.IN1
d[3] => Decoder0.IN0
seg[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
seg[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
seg[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
seg[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
seg[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
seg[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
seg[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
seg[7] <= <VCC>


|DPTrafficLight|int_div:inst1
clock => count_p[15].CLK
clock => count_p[14].CLK
clock => count_p[13].CLK
clock => count_p[12].CLK
clock => count_p[11].CLK
clock => count_p[10].CLK
clock => count_p[9].CLK
clock => count_p[8].CLK
clock => count_p[7].CLK
clock => count_p[6].CLK
clock => count_p[5].CLK
clock => count_p[4].CLK
clock => count_p[3].CLK
clock => count_p[2].CLK
clock => count_p[1].CLK
clock => count_p[0].CLK
clock => clk_p_r.CLK
clock => clock_out_r.CLK
clock_out <= clock_out_r.DB_MAX_OUTPUT_PORT_TYPE


|DPTrafficLight|TrafficLight:inst6
Reset => Load.ACLR
Reset => CounterH~2.IN1
Reset => State~15.IN1
Sensor => StateTransition~0.IN1
Sensor => StateTransition~1.IN1
Clk => Count0[3].CLK
Clk => Count0[2].CLK
Clk => Count0[1].CLK
Clk => Count0[0].CLK
Clk => Count1[3].CLK
Clk => Count1[2].CLK
Clk => Count1[1].CLK
Clk => Count1[0].CLK
Clk => Load.CLK
Clk => State~14.IN1
Numeral[0] <= Count0[0].DB_MAX_OUTPUT_PORT_TYPE
Numeral[1] <= Count0[1].DB_MAX_OUTPUT_PORT_TYPE
Numeral[2] <= Count0[2].DB_MAX_OUTPUT_PORT_TYPE
Numeral[3] <= Count0[3].DB_MAX_OUTPUT_PORT_TYPE
Numeral[4] <= Count1[0].DB_MAX_OUTPUT_PORT_TYPE
Numeral[5] <= Count1[1].DB_MAX_OUTPUT_PORT_TYPE
Numeral[6] <= Count1[2].DB_MAX_OUTPUT_PORT_TYPE
Numeral[7] <= Count1[3].DB_MAX_OUTPUT_PORT_TYPE
Light[0] <= Light~0.DB_MAX_OUTPUT_PORT_TYPE
Light[1] <= State.mrcy.DB_MAX_OUTPUT_PORT_TYPE
Light[2] <= State.mrcg.DB_MAX_OUTPUT_PORT_TYPE
Light[3] <= Light~0.DB_MAX_OUTPUT_PORT_TYPE
Light[4] <= State.mycr.DB_MAX_OUTPUT_PORT_TYPE
Light[5] <= State.mgcr.DB_MAX_OUTPUT_PORT_TYPE


|DPTrafficLight|int_div:inst14
clock => count_p[24].CLK
clock => count_p[23].CLK
clock => count_p[22].CLK
clock => count_p[21].CLK
clock => count_p[20].CLK
clock => count_p[19].CLK
clock => count_p[18].CLK
clock => count_p[17].CLK
clock => count_p[16].CLK
clock => count_p[15].CLK
clock => count_p[14].CLK
clock => count_p[13].CLK
clock => count_p[12].CLK
clock => count_p[11].CLK
clock => count_p[10].CLK
clock => count_p[9].CLK
clock => count_p[8].CLK
clock => count_p[7].CLK
clock => count_p[6].CLK
clock => count_p[5].CLK
clock => count_p[4].CLK
clock => count_p[3].CLK
clock => count_p[2].CLK
clock => count_p[1].CLK
clock => count_p[0].CLK
clock => clk_p_r.CLK
clock => clock_out_r.CLK
clock_out <= clock_out_r.DB_MAX_OUTPUT_PORT_TYPE