📄 prev_cmp_dptrafficlight.qmsg
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{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" { } { } 0 0 "Completed %1!s!" 0 0 "" 0}
{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "1 " "Warning: Following 1 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SEG\[7\] VCC " "Info: Pin SEG\[7\] has VCC driving its datain port" { } { { "DPTrafficLight.bdf" "" { Schematic "F:/DPA_4_TrafficLight/DPTrafficLight.bdf" { { 392 992 1168 408 "SEG\[7..0\]" "" } } } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "SEG\[7\]" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SEG[7] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SEG[7] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} } { } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" 0 0 "" 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "F:/DPA_4_TrafficLight/DPTrafficLight.fit.smsg " "Info: Generated suppressed messages file F:/DPA_4_TrafficLight/DPTrafficLight.fit.smsg" { } { } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1 Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "193 " "Info: Allocated 193 megabytes of memory during processing" { } { } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sun May 04 16:33:48 2008 " "Info: Processing ended: Sun May 04 16:33:48 2008" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Info: Elapsed time: 00:00:08" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Full Version " "Info: Version 7.1 Build 156 04/30/2007 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun May 04 16:33:50 2008 " "Info: Processing started: Sun May 04 16:33:50 2008" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off DPTrafficLight -c DPTrafficLight " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off DPTrafficLight -c DPTrafficLight" { } { } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" { } { } 0 0 "Assembler is generating device programming files" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "144 " "Info: Allocated 144 megabytes of memory during processing" { } { } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sun May 04 16:33:58 2008 " "Info: Processing ended: Sun May 04 16:33:58 2008" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Info: Elapsed time: 00:00:08" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Full Version " "Info: Version 7.1 Build 156 04/30/2007 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun May 04 16:34:00 2008 " "Info: Processing started: Sun May 04 16:34:00 2008" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off DPTrafficLight -c DPTrafficLight --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off DPTrafficLight -c DPTrafficLight --timing_analysis_only" { } { } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "Clock " "Info: Assuming node \"Clock\" is an undefined clock" { } { { "DPTrafficLight.bdf" "" { Schematic "F:/DPA_4_TrafficLight/DPTrafficLight.bdf" { { 392 -88 80 408 "Clock" "" } } } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "Clock" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} } { } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "16 " "Warning: Found 16 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "KeyDebounce:inst5\|inst4 " "Info: Detected ripple clock \"KeyDebounce:inst5\|inst4\" as buffer" { } { { "KeyDebounce.bdf" "" { Schematic "F:/DPA_4_TrafficLight/KeyDebounce.bdf" { { 264 656 720 344 "inst4" "" } } } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "KeyDebounce:inst5\|inst4" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "KeyDebounce:inst5\|inst " "Info: Detected ripple clock \"KeyDebounce:inst5\|inst\" as buffer" { } { { "KeyDebounce.bdf" "" { Schematic "F:/DPA_4_TrafficLight/KeyDebounce.bdf" { { 264 240 304 344 "inst" "" } } } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "KeyDebounce:inst5\|inst" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "KeyDebounce:inst5\|inst3~23 " "Info: Detected gated clock \"KeyDebounce:inst5\|inst3~23\" as buffer" { } { { "KeyDebounce.bdf" "" { Schematic "F:/DPA_4_TrafficLight/KeyDebounce.bdf" { { 176 760 864 288 "inst3" "" } } } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "KeyDebounce:inst5\|inst3~23" } } } } } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "KeyDebounce:inst5\|inst1 " "Info: Detected ripple clock \"KeyDebounce:inst5\|inst1\" as buffer" { } { { "KeyDebounce.bdf" "" { Schematic "F:/DPA_4_TrafficLight/KeyDebounce.bdf" { { 264 344 408 344 "inst1" "" } } } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "KeyDebounce:inst5\|inst1" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "KeyDebounce:inst5\|inst2 " "Info: Detected ripple clock \"KeyDebounce:inst5\|inst2\" as buffer" { } { { "KeyDebounce.bdf" "" { Schematic "F:/DPA_4_TrafficLight/KeyDebounce.bdf" { { 264 448 512 344 "inst2" "" } } } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "KeyDebounce:inst5\|inst2" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "KeyDebounce:inst5\|inst5 " "Info: Detected ripple clock \"KeyDebounce:inst5\|inst5\" as buffer" { } { { "KeyDebounce.bdf" "" { Schematic "F:/DPA_4_TrafficLight/KeyDebounce.bdf" { { 264 552 616 344 "inst5" "" } } } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "KeyDebounce:inst5\|inst5" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "KeyDebounce:inst13\|inst4 " "Info: Detected ripple clock \"KeyDebounce:inst13\|inst4\" as buffer" { } { { "KeyDebounce.bdf" "" { Schematic "F:/DPA_4_TrafficLight/KeyDebounce.bdf" { { 264 656 720 344 "inst4" "" } } } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "KeyDebounce:inst13\|inst4" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "KeyDebounce:inst13\|inst " "Info: Detected ripple clock \"KeyDebounce:inst13\|inst\" as buffer" { } { { "KeyDebounce.bdf" "" { Schematic "F:/DPA_4_TrafficLight/KeyDebounce.bdf" { { 264 240 304 344 "inst" "" } } } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "KeyDebounce:inst13\|inst" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "KeyDebounce:inst13\|inst3~23 " "Info: Detected gated clock \"KeyDebounce:inst13\|inst3~23\" as buffer" { } { { "KeyDebounce.bdf" "" { Schematic "F:/DPA_4_TrafficLight/KeyDebounce.bdf" { { 176 760 864 288 "inst3" "" } } } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "KeyDebounce:inst13\|inst3~23" } } } } } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "KeyDebounce:inst13\|inst1 " "Info: Detected ripple clock \"KeyDebounce:inst13\|inst1\" as buffer" { } { { "KeyDebounce.bdf" "" { Schematic "F:/DPA_4_TrafficLight/KeyDebounce.bdf" { { 264 344 408 344 "inst1" "" } } } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "KeyDebounce:inst13\|inst1" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "int_div:inst\|clock_out_r " "Info: Detected ripple clock \"int_div:inst\|clock_out_r\" as buffer" { } { { "int_div.vhd" "" { Text "F:/DPA_4_TrafficLight/int_div.vhd" 87 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "int_div:inst\|clock_out_r" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "KeyDebounce:inst13\|inst2 " "Info: Detected ripple clock \"KeyDebounce:inst13\|inst2\" as buffer" { } { { "KeyDebounce.bdf" "" { Schematic "F:/DPA_4_TrafficLight/KeyDebounce.bdf" { { 264 448 512 344 "inst2" "" } } } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "KeyDebounce:inst13\|inst2" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "KeyDebounce:inst13\|inst5 " "Info: Detected ripple clock \"KeyDebounce:inst13\|inst5\" as buffer" { } { { "KeyDebounce.bdf" "" { Schematic "F:/DPA_4_TrafficLight/KeyDebounce.bdf" { { 264 552 616 344 "inst5" "" } } } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "KeyDebounce:inst13\|inst5" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "int_div:inst14\|clock_out_r " "Info: Detected ripple clock \"int_div:inst14\|clock_out_r\" as buffer" { } { { "int_div.vhd" "" { Text "F:/DPA_4_TrafficLight/int_div.vhd" 87 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "int_div:inst14\|clock_out_r" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "KeyDebounce:inst5\|inst3 " "Info: Detected gated clock \"KeyDebounce:inst5\|inst3\" as buffer" { } { { "KeyDebounce.bdf" "" { Schematic "F:/DPA_4_TrafficLight/KeyDebounce.bdf" { { 176 760 864 288 "inst3" "" } } } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "KeyDebounce:inst5\|inst3" } } } } } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "KeyDebounce:inst13\|inst3 " "Info: Detected gated clock \"KeyDebounce:inst13\|inst3\" as buffer" { } { { "KeyDebounce.bdf" "" { Schematic "F:/DPA_4_TrafficLight/KeyDebounce.bdf" { { 176 760 864 288 "inst3" "" } } } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "KeyDebounce:inst13\|inst3" } } } } } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} } { } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "Clock register int_div:inst14\|count_p\[1\] register int_div:inst14\|count_p\[6\] 120.64 MHz 8.289 ns Internal " "Info: Clock \"Clock\" has Internal fmax of 120.64 MHz between source register \"int_div:inst14\|count_p\[1\]\" and destination register \"int_div:inst14\|count_p\[6\]\" (period= 8.289 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.028 ns + Longest register register " "Info: + Longest register to register delay is 8.028 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns int_div:inst14\|count_p\[1\] 1 REG LC_X45_Y17_N4 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X45_Y17_N4; Fanout = 3; REG Node = 'int_div:inst14\|count_p\[1\]'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { int_div:inst14|count_p[1] } "NODE_NAME" } } { "int_div.vhd" "" { Text "F:/DPA_4_TrafficLight/int_div.vhd" 62 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.724 ns) + CELL(0.442 ns) 1.166 ns int_div:inst14\|LessThan0~973 2 COMB LC_X44_Y17_N0 1 " "Info: 2: + IC(0.724 ns) + CELL(0.442 ns) = 1.166 ns; Loc. = LC_X44_Y17_N0; Fanout = 1; COMB Node = 'int_div:inst14\|LessThan0~973'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.166 ns" { int_div:inst14|count_p[1] int_div:inst14|LessThan0~973 } "NODE_NAME" } } { "c:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1509 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.699 ns) + CELL(0.292 ns) 2.157 ns int_div:inst14\|LessThan0~975 3 COMB LC_X45_Y17_N1 2 " "Info: 3: + IC(0.699 ns) + CELL(0.292 ns) = 2.157 ns; Loc. = LC_X45_Y17_N1; Fanout = 2; COMB Node = 'int_div:inst14\|LessThan0~975'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.991 ns" { int_div:inst14|LessThan0~973 int_div:inst14|LessThan0~975 } "NODE_NAME" } } { "c:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1509 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.114 ns) 2.453 ns int_div:inst14\|LessThan0~976 4 COMB LC_X45_Y17_N2 1 " "Info: 4: + IC(0.182 ns) + CELL(0.114 ns) = 2.453 ns; Loc. = LC_X45_Y17_N2; Fanout = 1; COMB Node = 'int_div:inst14\|LessThan0~976'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.296 ns" { int_div:inst14|LessThan0~975 int_div:inst14|LessThan0~976 } "NODE_NAME" } } { "c:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1509 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.214 ns) + CELL(0.114 ns) 3.781 ns int_div:inst14\|LessThan0~978 5 COMB LC_X44_Y15_N6 1 " "Info: 5: + IC(1.214 ns) + CELL(0.114 ns) = 3.781 ns; Loc. = LC_X44_Y15_N6; Fanout = 1; COMB Node = 'int_div:inst14\|LessThan0~978'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.328 ns" { int_div:inst14|LessThan0~976 int_div:inst14|LessThan0~978 } "NODE_NAME" } } { "c:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1509 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.114 ns) 4.077 ns int_div:inst14\|LessThan0~981 6 COMB LC_X44_Y15_N7 1 " "Info: 6: + IC(0.182 ns) + CELL(0.114 ns) = 4.077 ns; Loc. = LC_X44_Y15_N7; Fanout = 1; COMB Node = 'int_div:inst14\|LessThan0~981'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.296 ns" { int_div:inst14|LessThan0~978 int_div:inst14|LessThan0~981 } "NODE_NAME" } } { "c:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1509 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.686 ns) + CELL(0.114 ns) 4.877 ns int_div:inst14\|LessThan0~979 7 COMB LC_X45_Y15_N9 2 " "Info: 7: + IC(0.686 ns) + CELL(0.114 ns) = 4.877 ns; Loc. = LC_X45_Y15_N9; Fanout = 2; COMB Node = 'int_div:inst14\|LessThan0~979'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.800 ns" { int_div:inst14|LessThan0~981 int_div:inst14|LessThan0~979 } "NODE_NAME" } } { "c:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1509 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.449 ns) + CELL(0.292 ns) 5.618 ns int_div:inst14\|LessThan0~980 8 COMB LC_X45_Y15_N8 25 " "Info: 8: + IC(0.449 ns) + CELL(0.292 ns) = 5.618 ns; Loc. = LC_X45_Y15_N8; Fanout = 25; COMB Node = 'int_div:inst14\|LessThan0~980'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.741 ns" { int_div:inst14|LessThan0~979 int_div:inst14|LessThan0~980 } "NODE_NAME" } } { "c:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1509 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.298 ns) + CELL(1.112 ns) 8.028 ns int_div:inst14\|count_p\[6\] 9 REG LC_X45_Y17_N9 3 " "Info: 9: + IC(1.298 ns) + CELL(1.112 ns) = 8.028 ns; Loc. = LC_X45_Y17_N9; Fanout = 3; REG Node = 'int_div:inst14\|count_p\[6\]'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.410 ns" { int_div:inst14|LessThan0~980 int_div:inst14|count_p[6] } "NODE_NAME" } } { "int_div.vhd" "" { Text "F:/DPA_4_TrafficLight/int_div.vhd" 62 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.594 ns ( 32.31 % ) " "Info: Total cell delay = 2.594 ns ( 32.31 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.434 ns ( 67.69 % ) " "Info: Total interconnect delay = 5.434 ns ( 67.69 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.028 ns" { int_div:inst14|count_p[1] int_div:inst14|LessThan0~973 int_div:inst14|LessThan0~975 int_div:inst14|LessThan0~976 int_div:inst14|LessThan0~978 int_div:inst14|LessThan0~981 int_div:inst14|LessThan0~979 int_div:inst14|LessThan0~980 int_div:inst14|count_p[6] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "8.028 ns" { int_div:inst14|count_p[1] int_div:inst14|LessThan0~973 int_div:inst14|LessThan0~975 int_div:inst14|LessThan0~976 int_div:inst14|LessThan0~978 int_div:inst14|LessThan0~981 int_div:inst14|LessThan0~979 int_div:inst14|LessThan0~980 int_div:inst14|count_p[6] } { 0.000ns 0.724ns 0.699ns 0.182ns 1.214ns 0.182ns 0.686ns 0.449ns 1.298ns } { 0.000ns 0.442ns 0.292ns 0.114ns 0.114ns 0.114ns 0.114ns 0.292ns 1.112ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clock destination 3.187 ns + Shortest register " "Info: + Shortest clock path from clock \"Clock\" to destination register is 3.187 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns Clock 1 CLK PIN_28 66 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 66; CLK Node = 'Clock'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { Clock } "NODE_NAME" } } { "DPTrafficLight.bdf" "" { Schematic "F:/DPA_4_TrafficLight/DPTrafficLight.bdf" { { 392 -88 80 408 "Clock" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.007 ns) + CELL(0.711 ns) 3.187 ns int_div:inst14\|count_p\[6\] 2 REG LC_X45_Y17_N9 3 " "Info: 2: + IC(1.007 ns) + CELL(0.711 ns) = 3.187 ns; Loc. = LC_X45_Y17_N9; Fanout = 3; REG Node = 'int_div:inst14\|count_p\[6\]'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.718 ns" { Clock int_div:inst14|count_p[6] } "NODE_NAME" } } { "int_div.vhd" "" { Text "F:/DPA_4_TrafficLight/int_div.vhd" 62 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 68.40 % ) " "Info: Total cell delay = 2.180 ns ( 68.40 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.007 ns ( 31.60 % ) " "Info: Total interconnect delay = 1.007 ns ( 31.60 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.187 ns" { Clock int_div:inst14|count_p[6] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.187 ns" { Clock Clock~out0 int_div:inst14|count_p[6] } { 0.000ns 0.000ns 1.007ns } { 0.000ns 1.469ns 0.711ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clock source 3.187 ns - Longest register " "Info: - Longest clock path from clock \"Clock\" to source register is 3.187 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns Clock 1 CLK PIN_28 66 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 66; CLK Node = 'Clock'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { Clock } "NODE_NAME" } } { "DPTrafficLight.bdf" "" { Schematic "F:/DPA_4_TrafficLight/DPTrafficLight.bdf" { { 392 -88 80 408 "Clock" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.007 ns) + CELL(0.711 ns) 3.187 ns int_div:inst14\|count_p\[1\] 2 REG LC_X45_Y17_N4 3 " "Info: 2: + IC(1.007 ns) + CELL(0.711 ns) = 3.187 ns; Loc. = LC_X45_Y17_N4; Fanout = 3; REG Node = 'int_div:inst14\|count_p\[1\]'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.718 ns" { Clock int_div:inst14|count_p[1] } "NODE_NAME" } } { "int_div.vhd" "" { Text "F:/DPA_4_TrafficLight/int_div.vhd" 62 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 68.40 % ) " "Info: Total cell delay = 2.180 ns ( 68.40 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.007 ns ( 31.60 % ) " "Info: Total interconnect delay = 1.007 ns ( 31.60 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.187 ns" { Clock int_div:inst14|count_p[1] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.187 ns" { Clock Clock~out0 int_div:inst14|count_p[1] } { 0.000ns 0.000ns 1.007ns } { 0.000ns 1.469ns 0.711ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.187 ns" { Clock int_div:inst14|count_p[6] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.187 ns" { Clock Clock~out0 int_div:inst14|count_p[6] } { 0.000ns 0.000ns 1.007ns } { 0.000ns 1.469ns 0.711ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.187 ns" { Clock int_div:inst14|count_p[1] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.187 ns" { Clock Clock~out0 int_div:inst14|count_p[1] } { 0.000ns 0.000ns 1.007ns } { 0.000ns 1.469ns 0.711ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" { } { { "int_div.vhd" "" { Text "F:/DPA_4_TrafficLight/int_div.vhd" 62 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" { } { { "int_div.vhd" "" { Text "F:/DPA_4_TrafficLight/int_div.vhd" 62 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.028 ns" { int_div:inst14|count_p[1] int_div:inst14|LessThan0~973 int_div:inst14|LessThan0~975 int_div:inst14|LessThan0~976 int_div:inst14|LessThan0~978 int_div:inst14|LessThan0~981 int_div:inst14|LessThan0~979 int_div:inst14|LessThan0~980 int_div:inst14|count_p[6] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "8.028 ns" { int_div:inst14|count_p[1] int_div:inst14|LessThan0~973 int_div:inst14|LessThan0~975 int_div:inst14|LessThan0~976 int_div:inst14|LessThan0~978 int_div:inst14|LessThan0~981 int_div:inst14|LessThan0~979 int_div:inst14|LessThan0~980 int_div:inst14|count_p[6] } { 0.000ns 0.724ns 0.699ns 0.182ns 1.214ns 0.182ns 0.686ns 0.449ns 1.298ns } { 0.000ns 0.442ns 0.292ns 0.114ns 0.114ns 0.114ns 0.114ns 0.292ns 1.112ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.187 ns" { Clock int_div:inst14|count_p[6] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.187 ns" { Clock Clock~out0 int_div:inst14|count_p[6] } { 0.000ns 0.000ns 1.007ns } { 0.000ns 1.469ns 0.711ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.187 ns" { Clock int_div:inst14|count_p[1] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.187 ns" { Clock Clock~out0 int_div:inst14|count_p[1] } { 0.000ns 0.000ns 1.007ns } { 0.000ns 1.469ns 0.711ns } "" } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "KeyDebounce:inst13\|inst Sensor Clock 1.201 ns register " "Info: tsu for register \"KeyDebounce:inst13\|inst\" (data pin = \"Sensor\", clock pin = \"Clock\") is 1.201 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.849 ns + Longest pin register " "Info: + Longest pin to register delay is 8.849 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns Sensor 1 PIN PIN_158 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_158; Fanout = 1; PIN Node = 'Sensor'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { Sensor } "NODE_NAME" } } { "DPTrafficLight.bdf" "" { Schematic "F:/DPA_4_TrafficLight/DPTrafficLight.bdf" { { 256 88 256 272 "Sensor" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(7.265 ns) + CELL(0.115 ns) 8.849 ns KeyDebounce:inst13\|inst 2 REG LC_X32_Y14_N0 2 " "Info: 2: + IC(7.265 ns) + CELL(0.115 ns) = 8.849 ns; Loc. = LC_X32_Y14_N0; Fanout = 2; REG Node = 'KeyDebounce:inst13\|inst'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.380 ns" { Sensor KeyDebounce:inst13|inst } "NODE_NAME" } } { "KeyDebounce.bdf" "" { Schematic "F:/DPA_4_TrafficLight/KeyDebounce.bdf" { { 264 240 304 344 "inst" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.584 ns ( 17.90 % ) " "Info: Total cell delay = 1.584 ns ( 17.90 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.265 ns ( 82.10 % ) " "Info: Total interconnect delay = 7.265 ns ( 82.10 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.849 ns" { Sensor KeyDebounce:inst13|inst } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "8.849 ns" { Sensor Sensor~out0 KeyDebounce:inst13|inst } { 0.000ns 0.000ns 7.265ns } { 0.000ns 1.469ns 0.115ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" { } { { "KeyDebounce.bdf" "" { Schematic "F:/DPA_4_TrafficLight/KeyDebounce.bdf" { { 264 240 304 344 "inst" "" } } } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clock destination 7.685 ns - Shortest register " "Info: - Shortest clock path from clock \"Clock\" to destination register is 7.685 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000⌨️ 快捷键说明
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